Memristor Based Event Driven Neuromorphic Nano-CMOS Processor

Abstract

‘Neuromorphic engineering’ has been showing significant developments in recent days. The word ‘neuromorphic’ was first coined by Caver Mead, which is morphing biological brain on-chip [1]. The main idea is to use the sub-threshold currents of transistors and mimic the biophysical properties that the neurons have. These brain-inspired neuromorphic computing systems have attracted research interest since they are alternate to classical von Neumann [2], computer architectures mainly because of the co-existence of memory and processing units. The renowned neuromorphic chips in the last few decades are Neurogrid [3], Truenorth [4], BrainScaleS [5], and SpiNNaker [6]. Memristors are the fourth fundamental passive-bipolar device, that links charge and flux non-linearly. When Chua coined the word ‘Memristor’ in the late 70s, there was no hint of the existence of the device [7]. Later when the physical existence of the device was shown by HP Labs, it sparked a new wave of enthusiasm among the neuromorphic community [8]. Properties such as non-volatile storage, nano-size existence, non-abrupt switching transition, continuously distributed resistance states, and repeatable behavior convinced the neuromorphic researcher to realize memristors as favorable synaptic elements for neuromorphic systems. In this scenario, the research activities carried out in this doctoral dissertation demonstrates a neuromorphic processing chip for event-driven learning, using memristors as synapses, which are integrated monolithically above the CMOS layers. Although memristors emerged as a potential synapse to solve the density challenge, scalability remains an important bottleneck. Neuromorphic systems should be made more scalable to realize large networks. To contribute to this, we focus on significant challenges in memristor-based neuromorphic hardware. They are- 1) Implementing an on-chip three-stage bulk-based calibration scheme for memristive crossbars and using its low-power inference for recognizing patterns using template matching, programming, and learning. 2) Designing a new current attenuator that is used for efficient crossbar read-outs with a scale-down factor of about 104. The thesis also demonstrates- characterization of three different memristors on various test-benches such as- ArC One Instrument, a full-custom test-PCB, and using probe station with semiconductor parameter analyzer.