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Ponencia
Bio-inspired analog parallel array processor chip with programmable spatio-temporal dynamics
(Institute of Electrical and Electronics Engineers, 2002)
A bio-inspired model for an analog parallel array processor (APAP), based on studies on the vertebrate retina, permits the realization of complex spatio-temporal dynamics in VLSI. This model mimics the way in which images ...
Ponencia
Mismatch-induced tradeoffs and scalability of mixed-signal vision chips
(Institute of Electrical and Electronics Engineers, 2002)
This paper explores different trade-offs associated with the design of analog VLSI chips. These trade-offs are related to the necessity of keeping the analog accuracy while taking advantage of the possibility of reducing ...
Ponencia
A processing element architecture for high-density focal plane analog programmable array processors
(Institute of Electrical and Electronics Engineers, 2002)
The architecture of the elementary Processing Element - PE- used in a recently designed 128×128 Focal Plane Analog Programmable Array Processor is presented. The PE architecture contains the required building blocks to ...
Ponencia
A multimode gray-scale CMOS optical sensor for visual computers
(Institute of Electrical and Electronics Engineers, 2002)
This paper presents a new multimode optical sensor architecture for the optical interface of Visual CNN (cellular neural net) chips. The sensor offers to the user the possibility of choosing the photo-sensitive device as ...
Ponencia
CMOS realization of a 2-layer CNN universal machine chip
(Institute of Electrical and Electronics Engineers, 2002)
Some of the features of the biological retina can be modelled by a cellular neural network (CNN) composed of two dynamically coupled layers of locally connected elementary nonlinear processors. In order to explore the ...
Ponencia
ACE16K: A 128×128 focal plane analog processor with digital I/O
(Institute of Electrical and Electronics Engineers, 2002)
This paper presents a new generation 128×128 focal-plane analog programmable array processor (FPAPAP), from a system level perspective, which has been manufactured in a 0.35 μm standard digital 1P-5M CMOS technology. The ...