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Mostrando ítems 111-120 de 153
Ponencia
Characterization of electrical crosstalk in 4T-APS arrays using TCAD simulations
(Institute of Electrical and Electronics Engineers, 2017)
TCAD simulations have been conducted on a CMOS image sensor in order to characterize the electrical component of the crosstalk between pixels through the study of the electric field distribution. The image sensor consists ...
Ponencia
A CMOS-3D reconfigurable architecture with in-pixel processing for feature detectors
(Institute of Electrical and Electronics Engineers, 2012)
This paper introduces a two-tier CMOS-3D architecture for generation of Gaussian pyramids, detection of extrema, and calculation of spatial derivatives in an image. Such tasks are included in modern feature detectors, which ...
Ponencia
A Sub-μVRms Chopper Front-End for ECoG Recording
(Institute of Electrical and Electronics Engineers, 2019)
This paper presents a low-noise, low-power fully differential chopper-modulated front-end circuit intended for ECoG signal recording. Among other features, it uses a subthreshold source-follower biquad in the forward path ...
Ponencia
A 76nW, 4kS/s 10-bit SAR ADC with offset cancellation for biomedical applications
(Institute of Electrical and Electronics Engineers, 2016)
This paper presents a 10-bit fully-differential rail-to-rail successive approximation (SAR) ADC designed for biomedical applications. The ADC, fabricated in a 180nm HV CMOS technology, features low switching energy consumption ...
Ponencia
In-pixel ADC for a vision architecture on CMOS-3D technology
(Institute of Electrical and Electronics Engineers, 2010)
This paper addresses the design of an 8-bit single-slope in-pixel ADC for a 3D chip architecture intended for airborne surveillance and reconnaissance applications. The 3D chip architecture comprises a sensor layer with a ...
Ponencia
High-Level Performance Evaluation of Object Detection Based on Massively Parallel Focal-Plane Acceleration Requiring Minimum Pixel Area Overhead
(Springer, 2016)
Smart CMOS image sensors can leverage the inherent data-level parallelism and regular computational flow of early vision by incorporating elementary processors at pixel level. However, it comes at the cost of extra area ...
Ponencia
Design of a smart SiPM based on focal-plane processing elements for improved spatial resolution in PET
(The International Society for Optics and Photonics, 2011)
Single-photon avalanche diodes are compatible with standard CMOS. It means that photo-multipliers for scintillation detectors in nuclear medicine (i. e. PET, SPECT) can be built in inexpensive technologies. These silicon ...
Ponencia
A 64-channel inductively-powered neural recording sensor array
(Institute of Electrical and Electronics Engineers, 2012)
This paper reports a 64-channel inductively powered neural recording sensor array. Neural signals are acquired, filtered, digitized and compressed in the channels. Additionally, each channel implements a local auto-calibration ...
Ponencia
A high dynamic range image sensor with linear response based on asynchronous event detection
(Institute of Electrical and Electronics Engineers, 2015)
This paper investigates the potential of an image sensor that combines event-based asynchronous outputs with conventional integration of photocurrents. Pixels voltages can be read out following a traditional approach with ...
Capítulo de Libro
Image Feature Extraction Acceleration
(Springer, 2016)
Image feature extraction is instrumental for most of the best-performing algorithms in computer vision. However, it is also expensive in terms of computational and memory resources for embedded systems due to the need of ...