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High-performance ΣΔ ADC for ADSL applications in 0.35μm CMOS digital technology
(Institute of Electrical and Electronics Engineers, 2001)
We present a ΣΔ modulator designed for ADSL applications in a 0.3Sμm CMOS pure digital technology. It employs a 4th-order 3-stage cascade architecture including both single-bit and multi-bit quantizers with programmable ...