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Mostrando ítems 1-10 de 21
Ponencia
Integer-based digital processor for the estimation of phase synchronization between neural signals
(Institute of Electrical and Electronics Engineers, 2016)
This paper reports a low area, low power, integer-based neural digital processor for the calculation of phase synchronization between two neural signals. The processor calculates the phase-frequency content of a signal by ...
Artículo
Single-Exposure HDR Technique Based on Tunable Balance Between Local and Global Adaptation
(Institute of Electrical and Electronics Engineers, 2016)
This brief describes a high-dynamic-range technique that compresses wide ranges of illuminations into the available signal range with a single exposure. An online analysis of the image histogram provides the sensor with ...
Ponencia
Hardware-Aware Performance Evaluation for the Co-Design of Image Sensors and Vision Algorithms
(Institute of Electrical and Electronics Engineers, 2016)
The top-down approach to system design allows obtaining separate specifications for each subsystem. In the case of vision systems, this means propagating system-level specifications down to particular specifications for ...
Ponencia
In-pixel Voltage-Controlled Ring-Oscillator for Phase Interpolation in ToF Image Sensors
(2016)
The design and measurements of a CMOS pseudodifferential voltage-controlled ring-oscillator (VCRO) are presented. It is aimed to act as time interpolator for arrayable picosecond time-to-digital convertors (TDC). This ...
Ponencia
Experimental Evidence of Power Efficiency due to Architecture in Cellular Processor Array Chips
(Institute of Electrical and Electronics Engineers, 2016)
Speeding up algorithm execution can be achieved by increasing the number of processing cores working in parallel. Of course, this speedup is limited by the degree to which the algorithm can be parallelized. Equivalently, ...
Tesis Doctoral
Diseño CMOS de un sistema de visión “on-chip” para aplicaciones de muy alta velocidad
(2016-02-08)
Esta Tesis presenta arquitecturas, circuitos y chips para el diseño de sensores de visión CMOS con procesamiento paralelo embebido. La Tesis reporta dos chips, en concreto: El chip Q-Eye; El chip Eye-RIS_VSoC.. Y dos ...
Artículo
Image Sensing Scheme Enabling Fully-Programmable Light Adaptation and Tone Mapping with a Single Exposure
(Institute of Electrical and Electronics Engineers, 2016)
This letter presents new insights into a high dynamic range (HDR) technique recently reported. We demonstrate that two intertwined photodiodes per pixel can perform tone mapping under unconstrained illumination conditions ...
Ponencia
Pixel-wise parameter adaptation for single-exposure extension of the image dynamic range
(Association for Computing Machinery, 2016)
High dynamic range imaging is central in application fields like surveillance, intelligent transportation and advanced driving assistance systems. In some scenarios, methods for dynamic range extension based on multiple ...
Ponencia
A 4-mode reconfigurable low noise amplifier for implantable neural recording channels
(Institute of Electrical and Electronics Engineers, 2016)
In this paper a reconfigurable implantable low noise amplifier for the recording of neural signals is presented. It is comprised by low-power and noise efficient current reuse OTAs in its direct path. The proposed architecture ...
Artículo
A Bio-Inspired Vision Sensor With Dual Operation and Readout Modes
(Institute of Electrical and Electronics Engineers, 2016)
This paper presents a novel event-based vision sensor with two operation modes: intensity mode and spatial contrast detection. They can be combined with two different readout approaches: pulse density modulation and ...