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Mostrando ítems 1-5 de 5
Ponencia
Experimental Body-input Three-stage DC offset Calibration Scheme for Memristive Crossbar
(IEEE, 2020)
Reading several ReRAMs simultaneously in a neuromorphic circuit increases power consumption and limits scalability. Applying small inference read pulses is a vain attempt when offset voltages of the read-out circuit are ...
Ponencia
Neuron fault tolerance in spiking neural networks
(Institute of Electrical and Electronics Engineers. IEEE, 2021)
The error-resiliency of Artificial Intelligence (AI) hardware accelerators is a major concern, especially when they are deployed in mission-critical and safety-critical applications. In this paper, we propose a neuron ...
Ponencia
Implementation of binary stochastic STDP learning using chalcogenide-based memristive devices
(IEEE, 2021-04)
The emergence of nano-scale memristive devices encouraged many different research areas to exploit their use in multiple applications. One of the proposed applications was to implement synaptic connections in bio-inspired ...
Artículo
Neuromorphic Low-Power Inference on Memristive Crossbars With On-Chip Offset Calibration
(IEEE, 2021-03)
Monolithic integration of silicon with nano-sized Redox-based resistive Random-Access Memory (ReRAM) devices opened the door to the creation of dense synaptic connections for bio-inspired neuromorphic circuits. One ...
Artículo
A CMOL-Like Memristor-CMOS Neuromorphic Chip-Core Demonstrating Stochastic Binary STDP
(Institute of Electrical and Electronics Engineers Inc., 2022-12)
The advent of nanoscale memristors raised hopes of being able to build CMOL (CMOS/nanowire/molecular) type ultra-dense in-memory-computing circuit architectures. In CMOL, nanoscale memristors would be fabricated at the ...