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Mostrando ítems 1-10 de 10
Artículo
Transistor-Level Synthesis of Pipeline Analog-to-Digital Converters Using a Design-Space Reduction Algorithm
(Institute of Electrical and Electronics Engineers, 2011)
A novel transistor-level synthesis procedure for pipeline ADCs is presented. This procedure is able to directly map high-level converter specifications onto transistor sizes and biasing conditions. It is based on the ...
Artículo
Accurate Settling-Time Modeling and Design Procedures for Two-Stage Miller-Compensated Amplifiers for Switched-Capacitor Circuits
(Institute of Electrical and Electronics Engineers, 2009)
We present modeling techniques for accurate estimation of settling errors in switched-capacitor (SC) circuits built with Miller-compensated operational transconductance amplifiers (OTAs). One distinctive feature of the ...
Ponencia
A 5.3mW, 2.4GHz ESD protected Low-Noise Amplifier in a 0.13μm RFCMOS technology
(Institute of Electrical and Electronics Engineers, 2007)
An Electrostatic Discharge (ESD) protected Low- Noise Amplifier (LNA) for the 2.4 GHz ISM band designed in a 0.13 mum standard RFCMOS technology is presented. The amplifier, including packaging effects, achieves 16.8 dB ...
Ponencia
A self-calibration circuit for a neural spike recording channel
(Institute of Electrical and Electronics Engineers, 2011)
This paper presents a self-calibration circuit for a neural spike recording channel. The proposed design tunes the bandwidth of the signal acquisition Band-Pass Filter (BPF), which suffers from process variations corners. ...
Ponencia
An auto-calibrated neural spike recording channel with feature extraction capabilities
(The International Society for Optics and Photonics, 2011)
This paper presents a power efficient architecture for a neural spike recording channel. The channel offers a selfcalibration operation mode and can be used both for signal tracking (to raw digitize the acquired neural ...
Ponencia
A power efficient neural spike recording channel with data bandwidth reduction
(Institute of Electrical and Electronics Engineers, 2011)
This paper presents a mixed-signal neural spike recording channel which features, as an added value, a simple and low-power data compression mechanism. The channel uses a band-limited differential low noise amplifier and ...
Ponencia
Simulation-based high-level synthesis of Nyquist-rate data converters using MATLAB/SIMULINK
(The International Society for Optical Engineering - SPIE, 2005)
This paper presents a toolbox for the simulation, optimization and high-level synthesis of Nyquist-rate Analog-to-Digital (A/D) and Digital-to-Analog (D/A) Converters in MATLAB®. The embedded simulator uses SIMULINK® C-coded ...
Ponencia
An Embedded 12-bit 80MS/s A/D/A Interface for Power-Line Communications in 0.13μm Pure Digital CMOS Technology
(Institute of Electrical and Electronics Engineers, 2005)
This paper presents an embedded interface, comprising both A/D and D/A converters, which has been implemented in a 0.13μm pure digital CMOS technology. The interface is integrated in a system for high-performance broad-band ...
Ponencia
Electrical-level synthesis of pipeline ADCs
(Institute of Electrical and Electronics Engineers, 2008)
This paper presents a design tool for the synthesis of pipeline ADCs which is able to optimally map high-level converter specifications, such as the required effective resolution, onto electrical-level parameters, i.e., ...
Artículo
A Low-Power Programmable Neural Spike Detection Channel With Embedded Calibration and Data Compression
(Institute of Electrical and Electronics Engineers, 2012)
This paper reports a programmable 400 μm pitch neural spike recording channel, fabricated in a 130 nm standard CMOS technology, which implements amplification, filtering, digitization, analog spike detection plus feature ...