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Analysis of error mechanisms in switched-current Sigma-Delta modulators [Article]
(Springer, 2004)
This paper presents a systematic analysis of the major switched-current (SI) errors and their influence on the performance degradation of ΣΔ Modulators (ΣΔMs). The study is presented in a hierarchical systematic way. First, ...
Reliable analysis of settling errors in SC integrators - application to high-speed low-power ΣΔ modulators design [Presentation]
(1999)
This paper presents a detailed study on the transient response of SC integrators taking into account the effects of amplifier finite gain-bandwidth product and slew-rate during, unlike previous models, both the integration ...
Using CAD Tools for the Automatic Design of Low-Power ΣΔ Modulators [Presentation]
(1997)
This paper illustrates the use of a CAD methodology to design a high-resolution 2nd-order ZA modulator with optimized power con- sumption.The fabricated prototype in 0.7um CMOS technology features 16.4-bit resolution at ...
A CMOS 110-dB@40-kS/s programmable-gain chopper-stabilized third-order 2-1 cascade sigma-selta modulator for low-power high-linearity automotive aensor ASICs [Article]
(Institute of Electrical and Electronics Engineers, 2005)
This paper describes a 0.35-μm CMOS chopper-stabilized switched-capacitor 2-1 cascade ΣΔ modulator for automotive sensor interfaces. The modulator architecture has been selected from an exhaustive comparison among multiple ...
High-level synthesis of switched-capacitor, switched-current and continuous-time ΣΔ modulators using SIMULINK-based time-domain behavioral models [Article]
(Institute of Electrical and Electronics Engineers, 2005)
This paper presents a high-level synthesis tool for ΣΔ Modulators (ΣΔMs) that combines an accurate SIMULINK-based time-domain behavioral simulator with a statistical optimization core. Three different circuit techniques ...
Highly Linear 2,5-V CMOS ΣΔ Modulator for ADSL+ [Article]
(Institute of Electrical and Electronics Engineers, 2004)
We present a 90-dB spurious-free dynamic range sigma–delta modulator (ΣΔM) for asymmetric digital subscriber line applications (both ADSL and ADSL+), with up to a 4.4-MS/s digital output rate. It uses a cascade (MASH) ...
Fourth-order cascade SC ΣΔ modulators: a comparative study [Article]
(Institute of Electrical and Electronics Engineers, 1998)
Fourth-order cascade ΣΔ modulators are very well suited for IC implementation using analog sampled-data circuits because of their robust, stable operation and their capability to achieve high resolution and wide bandwidth ...
A 14-bit 4-MS/s Multi-bit Cascade Sigma-Delta Modulator in CMOS 0.35-um Digital Technology [Presentation]
(2000)
This paper presents a 4th-order 3-stage cascade SD modulator that achieves 14-bit dynamic range at 4MS/s using low oversampling ratio. It includes a programmable multi-bit quantizer in the last stage, providing 2-, 3-, ...
Selection of test techniques for high-resolution ΣΔ modulators [Presentation]
(2000)
This paper introduces a new tool which allows the evaluation of different test techniques in a complete impartial manner. This tool has been applied to the selection of the best test technique for their application to ...