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Ponencia
An Experimentally-Validated Verilog-A SPAD Model Extracted from TCAD Simulation
(Institute of Electrical and Electronics Engineers, 2018)
Single-photon avalanche diodes (SPAD) are photodetectors with exceptional characteristics. This paper proposes a new approach to model them in Verilog-A HDL with the help of a powerful tool: TCAD simulation. Besides, to ...
Artículo
Characterization-Based Modeling of Retriggering and Afterpulsing for Passively Quenched CMOS SPADs
(Institute of Electrical and Electronics Engineers, 2019)
The current trend in the design of systems based on CMOS SPADs is to adopt smaller technological nodes, allowing the co-integration of additional electronics for the implementation of complex digital systems on chip. Due ...
Artículo
A 4.2–13.2 V, on-chip, regulated, DC–DC converter in a standard 1.8V/3.3V CMOS process
(Elsevier, 2023)
This paper presents a fully on-chip HV-regulated DC–DC boost converter for the power management unit of an electrical neural stimulator. The core of the DC–DC converter consists of a 4x4 array of individually-configurable ...
Artículo
On the Analysis and Detection of Flames Withan Asynchronous Spiking Image Sensor
(IEEE, 2018)
We have investigated the capabilities of a customasynchronous spiking image sensor operating in the NearInfrared band to study flame radiation emissions, monitortheir transient activity, ...
Ponencia
Characterization of electrical crosstalk in 4T-APS arrays using TCAD simulations
(Institute of Electrical and Electronics Engineers, 2017)
TCAD simulations have been conducted on a CMOS image sensor in order to characterize the electrical component of the crosstalk between pixels through the study of the electric field distribution. The image sensor consists ...
Artículo
A Fully Integrated, Power-Efficient, 0.07–2.08 mA, High-Voltage Neural Stimulator in a Standard CMOS Process
(MDPI, 2022)
This paper presents a fully integrated high-voltage (HV) neural stimulator with on-chip HV generation. It consists of a neural stimulator front-end that delivers stimulation currents up to 2.08 mA with 5 bits resolution ...
Artículo
A High-voltage Floating Level Shifter for a Multi-stage Charge-pump in a Standard 1.8 V/3.3 V CMOS Process
(Elsevier, 2022)
This paper proposes a high-voltage floating level shifter with a periodically-refreshed charge pump topology. Designed and fabricated in a standard 1.8 V/3.3 V CMOS process, the circuit can withstand shifting voltages from ...