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Ponencia
A prototype tool for optimum analog sizing using simulated annealing
(Institute of Electrical and Electronics Engineers, 1992)
It is shown that using simulated annealing in combination with electrical simulation provides a powerful tool allowing unexperienced designer to size complex analogue building blocks starting from scratch. A cost function ...
Ponencia
Frequency tuning loop for VCOs
(Institute of Electrical and Electronics Engineers, 1991)
A frequency tuning circuit is introduced for VCOs (voltage-controlled oscillators) so that the final relationship between oscillating frequency and input control voltage is fixed and independent of nonidealities. This ...
Artículo
CMOS OTA-C high-frequency sinusoidal oscillators
(Institute of Electrical and Electronics Engineers, 1991)
Several topology families are given to implement practical CMOS sinusoidal oscillators by using operational transconductance amplifier-capacitor (OTA-C) techniques. Design techniques are proposed taking into account the ...
Ponencia
Design of an analog/digital truly random number generator
(Institute of Electrical and Electronics Engineers, 1990)
An analog-digital system is presented for the generation of truly random (aperiodic) digital sequences. This model is based on a very simple piecewise-linear discrete map which is suitable for implementation using monolithic ...
Artículo
Smart-Pixel Cellular Neural Networks in Analog Current-Mode CMOS Technology
(Institute of Electrical and Electronics Engineers, 1994)
This paper presents a systematic approach to design CMOS chips with concurrent picture acquisition and processing capabilities. These chips consist of regular arrangements of elementary units, called smart pixels. Light ...
Ponencia
A Model for VLSI implementation of CNN image processing chips using current-mode techniques
(Institute of Electrical and Electronics Engineers, 1993)
A new Cellular Neural Network model is proposed which allows simpler and faster VLSI implementation than previous models. Current-mode building blocks are presented for the design of CMOS image preprocessing chips (feature ...
Ponencia
Very high frequency CMOS OTA-C quadrature oscillators
(Institute of Electrical and Electronics Engineers, 1990)
An approach to the design of high-frequency monolithic voltage-controlled oscillators using operational transconductance amplifiers and capacitors is given. Results from two 3 μm CMOS prototypes are presented. Both frequency ...
Ponencia
Some design trade-offs for large CNN chips using small-size transistors
(Institute of Electrical and Electronics Engineers, 1997)
Small-size MOS transistors (MOST) exhibit a bunch of second-order effects which limit their application to design Cellular Neural Network (CNN) chips. The inverse dependency of mismatch with transistor sizes may result in ...
Ponencia
Tool for fast mismatch analysis of analog circuits
(Institute of Electrical and Electronics Engineers, 1995)
A tool is presented that evaluates statistical deviations in performance characteristics of analog circuits, starting from statistical deviations in the technological parameters of MOS transistors. Performance is demonstrated ...
Artículo
A CMOS analog adaptive BAM with on-chip learning and weight refreshing
(Institute of Electrical and Electronics Engineers, 1993)
In this paper we will extend the transconductance-mode (T-mode) approach [1] to implement analog continuous-time neural network hardware systems to include on-chip Hebbian learning and on-chip analog weight storage capability. ...