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Mostrando ítems 51-60 de 74
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On simplification techniques for symbolic analysis of analog integrated circuits
(Institute of Electrical and Electronics Engineers, 1992)
This paper addresses the topic of formula simplification for symbolic analyzers. Previously reported criteria for flat analysis approaches are briefly reviewed and their limitations illustrated via examples of practical ...
Ponencia
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Redes e interconexiones de procesadores con capacidad de tolerancia a fallos
(Universidad Politécnica de Madrid, 1992)
Se describe una familia de redes de interconexión para sistemas multiprocesadores. Estas redes utilizan buses múltiples estructurados en varios niveles e incorporan el concepto de tolerancia a fallos mediante redundancia ...
Artículo
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Analysis of Metastable Operation in a CMOS Dynamic D-Latch
(Springer, 1997)
Nowadays, metastability is becoming a serious problem in high-performance VLSI design, mainly due to the relatively-high probability of error when a bistable circuit operates at high frequencies. As far as we know, there ...
Artículo
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Circuits and Systems Letters: A Novel SC Oscillator
(Institute of Electrical and Electronics Engineers, 1984)
Ponencia
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VLSI implementation of a transconductance mode continuous BAM with on chip learning and dynamic analog memory
(Institute of Electrical and Electronics Engineers, 1991)
In this paper we present a complete VLSI Continuous-Time Bidirectional Associative Memory (BAM). The short term memory (STM) section is implemented using small transconductance four quadrant multipliers, and capacitors for ...
Ponencia
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An advanced symbolic analyzer for the automatic generation of analog circuit design equations
(Institute of Electrical and Electronics Engineers, 1991)
A tool for symbolic analysis of analog integrated circuits is presented featuring accurate simplification, pole/zero extraction, and tools for parametric AC circuit characterization. The program, called ASAP, uses signal ...
Ponencia
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New CMOS VLSI Linear Self-Timed Architectures
(1995)
The implementation of digital signal processor circuits via self-timed techniques is currently a valid altemative to solve some problems encountered in synchronous VLSI circuits. However; a main difference between ...
Ponencia
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A prototype tool for optimum analog sizing using simulated annealing
(Institute of Electrical and Electronics Engineers, 1992)
It is shown that using simulated annealing in combination with electrical simulation provides a powerful tool allowing unexperienced designer to size complex analogue building blocks starting from scratch. A cost function ...
Ponencia
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Frequency tuning loop for VCOs
(Institute of Electrical and Electronics Engineers, 1991)
A frequency tuning circuit is introduced for VCOs (voltage-controlled oscillators) so that the final relationship between oscillating frequency and input control voltage is fixed and independent of nonidealities. This ...
Artículo
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CMOS OTA-C high-frequency sinusoidal oscillators
(Institute of Electrical and Electronics Engineers, 1991)
Several topology families are given to implement practical CMOS sinusoidal oscillators by using operational transconductance amplifier-capacitor (OTA-C) techniques. Design techniques are proposed taking into account the ...