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dc.creatorTorralba Silgado, Antonio Jesúses
dc.creatorChávez Orzaez, Jorge Jesúses
dc.creatorGarcía Franquelo, Leopoldoes
dc.date.accessioned2021-03-24T14:15:04Z
dc.date.available2021-03-24T14:15:04Z
dc.date.issued2016
dc.identifier.citationTorralba Silgado, A.J., Chávez Orzaez, J.J. y García Franquelo, L. (2016). FASY: A fuzzy-logic based tool for analog synthesis. IEEE Transactions on Computer-Aided Design of Integrated Circuits, 15 (7), 705-715.
dc.identifier.urihttps://hdl.handle.net/11441/106567
dc.description.abstractA CAD tool for analog circuit synthesis is presented. This tool, called FASY, uses fuzzy–logic based reasoning to select one topology among a fixed set of alternatives. For the selected topology, a two–phase optimizer sizes all elements to satisfy the performance constrains minimizing a cost function. In FASY, the decision rules used in the topology selection process are introduced by an expert designer or automatically generated by means of a learning process that uses the optimizer mentioned above. The capability of learning topology selection rules by experience, is unique in FASY. Practical examples demonstrate the tool ability of this tool to learn topology selection rules and to synthesize analog cells with different circuit topologies.es
dc.formatapplication/pdfes
dc.format.extent11 p.es
dc.language.isoenges
dc.publisherInstitute of Electrical and Electronics Engineers (IEEE)es
dc.relation.ispartofIEEE Transactions on Computer-Aided Design of Integrated Circuits, 15 (7), 705-715.
dc.rightsAttribution-NonCommercial-NoDerivatives 4.0 Internacional*
dc.rights.urihttp://creativecommons.org/licenses/by-nc-nd/4.0/*
dc.subjectAnalog synthesises
dc.subjectTopology selection rulees
dc.subjectLearning processes
dc.titleFASY: A fuzzy-logic based tool for analog synthesises
dc.typeinfo:eu-repo/semantics/articlees
dcterms.identifierhttps://ror.org/03yxnpp24
dc.type.versioninfo:eu-repo/semantics/submittedVersiones
dc.rights.accessRightsinfo:eu-repo/semantics/openAccesses
dc.contributor.affiliationUniversidad de Sevilla. Departamento de Ingeniería Electrónicaes
dc.relation.publisherversionhttps://ieeexplore.ieee.org/abstract/document/503939es
dc.identifier.doi10.1109/43.503939es
dc.journaltitleIEEE Transactions on Computer-Aided Design of Integrated Circuitses
dc.publication.volumen15es
dc.publication.issue7es
dc.publication.initialPage705es
dc.publication.endPage715es
dc.identifier.sisius6536611es

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