dc.creator | Torralba Silgado, Antonio Jesús | es |
dc.creator | Chávez Orzaez, Jorge Jesús | es |
dc.creator | García Franquelo, Leopoldo | es |
dc.date.accessioned | 2021-03-24T14:15:04Z | |
dc.date.available | 2021-03-24T14:15:04Z | |
dc.date.issued | 2016 | |
dc.identifier.citation | Torralba Silgado, A.J., Chávez Orzaez, J.J. y García Franquelo, L. (2016). FASY: A fuzzy-logic based tool for analog synthesis. IEEE Transactions on Computer-Aided Design of Integrated Circuits, 15 (7), 705-715. | |
dc.identifier.uri | https://hdl.handle.net/11441/106567 | |
dc.description.abstract | A CAD tool for analog circuit synthesis is presented. This tool, called FASY, uses fuzzy–logic based reasoning to select one topology among a fixed set of alternatives. For the selected topology, a two–phase optimizer sizes all elements to satisfy the performance constrains minimizing a cost function. In FASY, the decision rules used in the topology selection process are introduced by an expert designer or automatically generated by means of a learning process that uses the optimizer mentioned above. The capability of learning topology selection rules by experience, is unique in FASY. Practical examples demonstrate the tool ability of this tool to learn topology selection rules and to synthesize analog cells with different circuit topologies. | es |
dc.format | application/pdf | es |
dc.format.extent | 11 p. | es |
dc.language.iso | eng | es |
dc.publisher | Institute of Electrical and Electronics Engineers (IEEE) | es |
dc.relation.ispartof | IEEE Transactions on Computer-Aided Design of Integrated Circuits, 15 (7), 705-715. | |
dc.rights | Attribution-NonCommercial-NoDerivatives 4.0 Internacional | * |
dc.rights.uri | http://creativecommons.org/licenses/by-nc-nd/4.0/ | * |
dc.subject | Analog synthesis | es |
dc.subject | Topology selection rule | es |
dc.subject | Learning process | es |
dc.title | FASY: A fuzzy-logic based tool for analog synthesis | es |
dc.type | info:eu-repo/semantics/article | es |
dcterms.identifier | https://ror.org/03yxnpp24 | |
dc.type.version | info:eu-repo/semantics/submittedVersion | es |
dc.rights.accessRights | info:eu-repo/semantics/openAccess | es |
dc.contributor.affiliation | Universidad de Sevilla. Departamento de Ingeniería Electrónica | es |
dc.relation.publisherversion | https://ieeexplore.ieee.org/abstract/document/503939 | es |
dc.identifier.doi | 10.1109/43.503939 | es |
dc.journaltitle | IEEE Transactions on Computer-Aided Design of Integrated Circuits | es |
dc.publication.volumen | 15 | es |
dc.publication.issue | 7 | es |
dc.publication.initialPage | 705 | es |
dc.publication.endPage | 715 | es |
dc.identifier.sisius | 6536611 | es |