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Mostrando ítems 1-10 de 91
Ponencia
Building Blocks for Spikes Signals Processing
(IEEE Computer Society, 2010)
Neuromorphic engineers study models and implementations of systems that mimic neurons behavior in the brain. Neuro-inspired systems commonly use spikes to represent information. This representation has several advantages: ...
Ponencia
On the AER Convolution Processors for FPGA
(IEEE Computer Society, 2010)
Image convolution operations in digital computer systems are usually very expensive operations in terms of resource consumption (processor resources and processing time) for an efficient Real-Time application. In these ...
Ponencia
An AER handshake-less modular infrastructure PCB with x8 2.5Gbps LVDS serial links
(IEEE Computer Society, 2014)
Nowadays spike-based brain processing emulation is taking off. Several EU and others worldwide projects are demonstrating this, like SpiNNaker, BrainScaleS, FACETS, or NeuroGrid. The larger the brain process emulation ...
Ponencia
AER tools for Communications and Debugging
(IEEE Computer Society, 2006)
Address-event-representation (AER) is a communications protocol for transferring spikes between bio-inspired chips. Such systems may consist of a hierarchical structure with several chips that transmit spikes among them ...
Ponencia
AER image filtering
(SPIE Digital LIbrary, 2007-05)
Address Event Representation (AER) is an emergent neuromorphic interchip communication protocol that allows realtime virtual massive connectivity among huge number of neurons located on different chips [1]. By exploiting ...
Ponencia
FPGA Implementations Comparison of Neuro-cortical Inspired Convolution Processors for Spiking Systems
(Springer, 2009)
Image convolution operations in digital computer systems are usually very expensive operations in terms of resource consumption (processor resources and processing time) for an efficient Real-Time application. In ...
Ponencia
Visual Spike-based Convolution Processing with a Cellular Automata Architecture
(IEEE Computer Society, 2010)
this paper presents a first approach for implementations which fuse the Address-Event-Representation (AER) processing with the Cellular Automata using FPGA and AER-tools. This new strategy applies spike-based ...
Ponencia
PCI to AER Hardware/Software interface for Real- Time Vision processing
(IEEE, 2005-06)
In this paper we present a mechanism that allows the coprocessing of video in real-time based into Address-Event-Representation (A ER) convolutions chips. Several software methods fur generating synthetic AEK streams from ...
Artículo
Application of bus emulation techniques to the design of a PCI/MC68000 bridge
(Elsevier, 2002)
Bridges easy the interconnection and communication of devices that operate using different buses. In fact, we can see a computer as a hierarchy of buses to which devices are connected. In this paper we design a PCI/MC68000 ...
Ponencia
High-speed image processing with AER-based components
(IEEE Computer Society, 2006)
A high speed sample image processing application using AER-based components is presented. The setup objective is to distinguish between two propellers of different shape rotating at high speed (around 1000 revolutions/sec) ...