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Ponencia
Using virtual potential fields for electric wheelchair guidance
(IEEE Computer Society, 2002)
TetraNauta is an electric wheelchair guidance system intended for people with heavy motion impairments (such as persons with tetraplegia). It is specially useful when impairments also affect wheelchair steering as it is ...
Ponencia
AER tools for Communications and Debugging
(IEEE Computer Society, 2006)
Address-event-representation (AER) is a communications protocol for transferring spikes between bio-inspired chips. Such systems may consist of a hierarchical structure with several chips that transmit spikes among them ...
Artículo
An eLearning Standard Approach for Supporting PBL in Computer Engineering
(IEEE Computer Society, 2009)
Problem-based learning (PBL) has proved to be a highly successful pedagogical model in many fields, although it is not that common in computer engineering. PBL goes beyond the typical teaching methodology by promoting ...
Ponencia
TetraNauta: a intelligent wheelchair for users with very severe mobility restrictions
(IEEE Computer Society, 2002)
The TetraNauta project is a low cost, fully open steering system to allow people with heavy motor impairments to move in a known environments (hospitals, schools, home, etc.). It minimizes the steering effort, especially ...
Ponencia
On the Design of Ambient Intelligent Systems in the Context of Assistive Technologies
(Springer, 2004)
The design of Ambient Intelligent Systems (AISs) is discussed in the context of assistive technologies. The main issues include ubiquitous communications, context awareness, natural interactions and heterogeneity, which ...
Ponencia
Time-Recovering PCI-AER interface for Bio-inspired Spiking Systems
(SPIE: The International Society for Optics and Photonics, 2005)
Address Event Representation (AER) is an emergent neuromorphic interchip communication protocol that allows for real-time virtual massive connectivity between huge number neurons located on different chips. By exploiting high ...
Artículo
Chrono-Scheduling; a simplified dynamic scheduling algorithm for timing predictable processors
(World Scientific Connecting Great MInds, 2009)
We propose a simpler and latency-reduced instruction scheduler, called chronoscheduling algorithm, which avoids large and difficult instruction wake-up in order to reduce power consumption and latencies. The key idea of ...
Ponencia
Una herramienta didáctica para el estudio del código máquina en procesadores de 64 bits
(Universidad Politécnica de Madrid, 2000)
Ponencia
Generación de señales analógicas mediante PWM empleando un núcleo en tiempo real sobre una arquitectura PC sin elementos adicionales de entradasalida
(Universidad Politécnica de Madrid, 2000)
Artículo
A Path Following Control for Unicycle Robots
(John Wiley and Sons, 2001)
In this work we present a new path following control for unicycle robots that is applicable for almost all the possible desired paths and whose analysis is very straightforward. First we select the path following method ...