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Ponencia
Compact Calibration Circuit for Large Neuromorphic Arrays
(IEEE Computer Society, 2008)
Low current applications, like neuromorphic circuits, where operating currents can be as low as few nano amps or less, suffer from huge transistor mismatches, resulting in around or less than 1-bit precision. Here we ...
Ponencia
Homological Region Adjacency Tree for a 3D Binary Digital Image via HSF Model
(Springer, 2019)
Given a 3D binary digital image I, we define and compute an edge-weighted tree, called Homological Region Tree (or Hom-Tree, for short). It coincides, as unweighted graph, with the classical Region Adjacency Tree of ...
Ponencia
On the Designing of Spikes Band-Pass Filters for FPGA
(Springer, 2011)
In this paper we present two implementations of spike-based bandpass filters, which are able to reject out-of-band frequency components in the spike domain. First one is based on the use of previously designed ...
Artículo
Extending Amdahl's Law for the Cloud Computing Era
(IEEE Computer Society, 2016)
By extending Amdahl's law, software developers can weigh the pros and cons of moving their applications to the cloud.
Ponencia
Generación de señales analógicas mediante PWM empleando un núcleo en tiempo real sobre una arquitectura PC sin elementos adicionales de entradasalida
(Universidad Politécnica de Madrid, 2000)
Ponencia
Analysis of Bluetooth Transmission Delay in Personal Area Networks
(IEEE Computer Society, 2008)
Bluetooth is by far the most employed technology to develop practical applications of Wireless Personal Area Networks (WPAN). This paper studies the performance of Bluetooth transmissions that make use of the Bluetooth ...
Artículo
High-Performance Architecture for Binary-Tree-Based Finite State Machines
(IEEE Computer Society, 2018)
A binary-tree-based finite state machine (BT-FSM) is a state machine with a 1-bit input signal whose state transition graph is a binary tree. BT-FSMs are useful in those application areas where searching in a binary ...
Ponencia
Performance study of synthetic AER generation on CPUs for Real-Time Video based on Spikes
(ACM Digital Library, 2009-07)
Address-Event-Representation (AER) is a neuromorphic interchip communication protocol that allows for real-time virtual massive connectivity between huge number neurons located on different chips. When building multi-chip ...
Artículo
Dynamic Vision Sensor integration on FPGA-based CNN accelerators for high-speed visual classification
(Cornell University, 2019)
Deep-learning is a cutting edge theory that is being applied to many fields. For vision applications the Convolutional Neural Networks (CNN) are demanding significant accuracy for classification tasks. Numerous hardware ...
Artículo
Finite State Machines With Input Multiplexing: A Performance Study
(IEEE Computer Society, 2015)
Finite state machines with input multiplexing (FSMIMs) have been proposed in previous works as a technique for efficient mapping FSMs into ROM memory. In this paper, we propose a new architecture for implementing FSMIMs, ...