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Ponencia
Event-driven stereo vision with orientation filters
(IEEE Computer Society, 2014)
The recently developed Dynamic Vision Sensors (DVS) sense dynamic visual information asynchronously and code it into trains of events with sub-micro second temporal resolution. This high temporal precision makes the ...
Ponencia
A Mismatch Calibrated Bipolar Spatial Contrast AER Retina with Adjustable Contrast Threshold
(IEEE Computer Society, 2009)
Address Event Representation (AER) is an emergent technology for assembling modular multi-blocks bio-inspired sensory and processing systems. Visual sensors (retinae) are among the first AER modules to be reported since ...
Artículo
Artículo
Neuromorphic Low-Power Inference on Memristive Crossbars With On-Chip Offset Calibration
(IEEE, 2021-03)
Monolithic integration of silicon with nano-sized Redox-based resistive Random-Access Memory (ReRAM) devices opened the door to the creation of dense synaptic connections for bio-inspired neuromorphic circuits. One ...
Artículo
A modular current-mode high-precision winner-take-all circuit
(IEEE Computer Society, 1995)
In this paper we present a Winner-Take-All (WTA) circuit realized using current-mode circuit design techniques. The operation of the WTA is based on current comparators and current mirrors. Speed and precision is determined ...
Ponencia
On neuromorphic spiking architectures for asynchronous STDP memristive systems
(IEEE Computer Society, 2010)
Neuromorphic circuits and systems techniques have great potential for exploiting novel nanotechnology devices, which suffer from great parametric spread and high defect rate. In this paper we explore some potential ways ...
Artículo
An Instant-Startup Jitter-Tolerant Manchester- Encoding Serializer/Deserializer Scheme for Event-Driven Bit-Serial LVDS Interchip AER Links
(IEEE Computer Society, 2011)
This paper presents a serializer/deserializer scheme for asynchronous address event representation (AER) bit-serial interchip communications. Each serial AER (sAER) link uses four wires: a micro strip pair for low voltage ...
Ponencia
Hardware Implementation of Convolutional STDP for On-line Visual Feature Learning
(IEEE. Institute of Electrical and Electronics Engineers, 2017)
We present a highly hardware friendly STDP (Spike Timing Dependent Plasticity) learning rule for training Spiking Convolutional Cores in Unsupervised mode and training Fully Connected Classifiers in Supervised ...
Artículo
A Low-Power Current Mode Fuzzy-ART Cell
(IEEE Computer Society, 2006)
This paper presents a very large scale integration (VLSI) implementation of a low-power current-mode fuzzy-adaptive resonance theory (ART) cell. The cell is based on a compact new current source multibit memory cell ...
Ponencia
Spike-Based Convolutional Network for real-time processing
(IEEE Computer Society, 2010)
In this paper we propose the first bio-inspired sixlayer convolutional network (ConvNet) non-frame based that can be implemented with already physically available spikebased electronic devices. The system was designed ...