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Mostrando ítems 1-4 de 4
Artículo
Transistor-Level Synthesis of Pipeline Analog-to-Digital Converters Using a Design-Space Reduction Algorithm
(Institute of Electrical and Electronics Engineers, 2011)
A novel transistor-level synthesis procedure for pipeline ADCs is presented. This procedure is able to directly map high-level converter specifications onto transistor sizes and biasing conditions. It is based on the ...
Ponencia
A self-calibration circuit for a neural spike recording channel
(Institute of Electrical and Electronics Engineers, 2011)
This paper presents a self-calibration circuit for a neural spike recording channel. The proposed design tunes the bandwidth of the signal acquisition Band-Pass Filter (BPF), which suffers from process variations corners. ...
Ponencia
An auto-calibrated neural spike recording channel with feature extraction capabilities
(The International Society for Optics and Photonics, 2011)
This paper presents a power efficient architecture for a neural spike recording channel. The channel offers a selfcalibration operation mode and can be used both for signal tracking (to raw digitize the acquired neural ...
Ponencia
A power efficient neural spike recording channel with data bandwidth reduction
(Institute of Electrical and Electronics Engineers, 2011)
This paper presents a mixed-signal neural spike recording channel which features, as an added value, a simple and low-power data compression mechanism. The channel uses a band-limited differential low noise amplifier and ...