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Mostrando ítems 1-10 de 27
Ponencia
Integer-based digital processor for the estimation of phase synchronization between neural signals
(Institute of Electrical and Electronics Engineers, 2016)
This paper reports a low area, low power, integer-based neural digital processor for the calculation of phase synchronization between two neural signals. The processor calculates the phase-frequency content of a signal by ...
Ponencia
Self-calibration of neural recording sensors
(Institute of Electrical and Electronics Engineers, 2014)
This paper reports a calibration system for automatically adjusting the bandpass and gain characteristics of programmable E×G sensors. The calibration mechanism of the bandpass characteristic is based on a mixed-signal ...
Ponencia
Real-time phase correlation based integrated system for seizure detection
(The Society of Photo-Optical Instrumentation Engineers, 2017)
This paper reports a low area, low power, integer-based digital processor for the calculation of phase synchronization between two neural signals. The processor calculates the phase-frequency content of a signal by identifying ...
Artículo
Phase Synchronization Operator for On-Chip Brain Functional Connectivity Computation
(Institute of Electrical and Electronics Engineers, 2019)
This paper presents an integer-based digital processor for the calculation of phase synchronization between two neural signals. It is based on the measurement of time periods between two consecutive minima. The simplicity ...
Ponencia
Transformer based front-end for a low power 2.4 GHz transceiver
(Institute of Electrical and Electronics Engineers, 2010)
A low power transceiver architecture for the 2.4 GHz ISM band using a 1.0 V supply is presented. It employs a transformer to convert the 100 Ω antenna impedance to almost 1 kΩ and so facilitates a low power transmitter and ...
Ponencia
Artifact-Aware Analogue/Mixed-Signal Front-Ends for Neural Recording Applications
(Institute of Electrical and Electronics Engineers, 2019)
This paper presents a brief review of techniques to overcome the problems associated with artifacts in analog frontends for neural recording applications. These techniques are employed for handling Common-Mode (CM) ...
Artículo
Transistor-Level Synthesis of Pipeline Analog-to-Digital Converters Using a Design-Space Reduction Algorithm
(Institute of Electrical and Electronics Engineers, 2011)
A novel transistor-level synthesis procedure for pipeline ADCs is presented. This procedure is able to directly map high-level converter specifications onto transistor sizes and biasing conditions. It is based on the ...
Ponencia
A 4-mode reconfigurable low noise amplifier for implantable neural recording channels
(Institute of Electrical and Electronics Engineers, 2016)
In this paper a reconfigurable implantable low noise amplifier for the recording of neural signals is presented. It is comprised by low-power and noise efficient current reuse OTAs in its direct path. The proposed architecture ...
Artículo
System-Level Design of a 64-Channel Low Power Neural Spike Recording Sensor
(Institute of Electrical and Electronics Engineers, 2017)
This paper reports an integrated 64-channel neural spike recording sensor, together with all the circuitry to process and configure the channels, process the neural data, transmit via a wireless link the information and ...
Ponencia
A self-calibration circuit for a neural spike recording channel
(Institute of Electrical and Electronics Engineers, 2011)
This paper presents a self-calibration circuit for a neural spike recording channel. The proposed design tunes the bandwidth of the signal acquisition Band-Pass Filter (BPF), which suffers from process variations corners. ...