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Mostrando ítems 1-9 de 9
Artículo
A Chaotic Switched-Capacitor Circuit for 1/f Noise Generation
(Institute of Electrical and Electronics Engineers, 1992)
A switched-capacitor circuit is reported for the generation of 1 / fYnoise. The circuit is described by a chaotic first-order piecewise-finear discrete map which yields a hopping transition between regions of chaotic motions ...
Ponencia
Application of piecewise-linear switched-capacitor circuits for random number generation
(Institute of Electrical and Electronics Engineers, 1989)
An unconventional application of switched-capacitor (SC) circuits is discussed. A systematic method for the design of piecewise-linear (PL) parasitic-insensitive SC chaotic discrete maps is given. A simple circuit which ...
Artículo
A switched-capacitor broadband noise generator for CMOS VLSI
(Institution of Engineering and Technology, 1991)
A switched-capacitor circuit is reported for the generation of broadband white noise in MOS VLSI. It is based on the implementation of a very simple chaotic discrete-time system. The concept is demonstrated via a 3ftm CMOS ...
Artículo
Current-Mode Techniques for the Implementation of Continuous- and Discrete-Time Cellular Neural Networks
(Institute of Electrical and Electronics Engineers, 1993)
This paper presents a unified, comprehensive approach to the design of continuous-time (CT) and discrete-time (DT) cellular neural networks (CNN) using CMOS current-mode analog techniques. The net input signals are ...
Ponencia
Switched-current techniques for image processing Cellular Neural Networks in MOS VLSI
(Institute of Electrical and Electronics Engineers, 1992)
An architecture and related building blocks are presented for the realization of image processing tasks using current-mode analog-digital circuits. The architecture is based on the Cellular Neural Network paradigm while ...
Ponencia
Design of an analog/digital truly random number generator
(Institute of Electrical and Electronics Engineers, 1990)
An analog-digital system is presented for the generation of truly random (aperiodic) digital sequences. This model is based on a very simple piecewise-linear discrete map which is suitable for implementation using monolithic ...
Artículo
Smart-Pixel Cellular Neural Networks in Analog Current-Mode CMOS Technology
(Institute of Electrical and Electronics Engineers, 1994)
This paper presents a systematic approach to design CMOS chips with concurrent picture acquisition and processing capabilities. These chips consist of regular arrangements of elementary units, called smart pixels. Light ...
Ponencia
A Model for VLSI implementation of CNN image processing chips using current-mode techniques
(Institute of Electrical and Electronics Engineers, 1993)
A new Cellular Neural Network model is proposed which allows simpler and faster VLSI implementation than previous models. Current-mode building blocks are presented for the design of CMOS image preprocessing chips (feature ...
Ponencia
Some design trade-offs for large CNN chips using small-size transistors
(Institute of Electrical and Electronics Engineers, 1997)
Small-size MOS transistors (MOST) exhibit a bunch of second-order effects which limit their application to design Cellular Neural Network (CNN) chips. The inverse dependency of mismatch with transistor sizes may result in ...