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Mostrando ítems 1-5 de 5
Artículo
A 0.8-μm CMOS two-dimensional programmable mixed-signal focal-plane array processor with on-chip binary imaging and instructions storage
(Institute of Electrical and Electronics Engineers, 1997)
This paper presents a CMOS chip for the parallel acquisition and concurrent analog processing of two-dimensional (2-D) binary images. Its processing function is determined by a reduced set of 19 analog coefficients whose ...
Artículo
A Bio-Inspired Two-Layer Mixed-Signal Flexible Programmable Chip for Early Vision
(Institute of Electrical and Electronics Engineers, 2003)
A bio-inspired model for an analog programmable array processor (APAP), based on studies on the vertebrate retina, has permitted the realization of complex programmable spatio-temporal dynamics in VLSI. This model mimics ...
Ponencia
CNN technology in action
(Institute of Electrical and Electronics Engineers, 2000)
Two Cellular Neural Net Universal Machine (CNN-UM) prototypes are demonstrated in action. The first one is the latest 4096 cell-processor, analog I/O, analogic CNN visual microprocessor, on which online video image processing ...
Artículo
An 0.5-μm CMOS analog random access memory chip for TeraOPS speed multimedia video processing
(Institute of Electrical and Electronics Engineers, 1999)
Data compressing, data coding, and communications in object-oriented multimedia applications like telepresence, computer-aided medical diagnosis, or telesurgery require an enormous computing power - in the order of trillions ...
Ponencia
A 0.5 /spl mu/m CMOS CNN analog random access memory chip for massive image processing
(Institute of Electrical and Electronics Engineers, 1998)
An analog RAM has been designed to act as a cache memory for a CNN Universal Machine. Hence, all the non-standard chips are available for the CNN Chipset architecture. Time-multiplexed analog routines in the CNN processor ...