Buscar
Mostrando ítems 1-10 de 21
Ponencia
A mixed-signal early vision chip with embedded image and programming memories and digital I/O
(The International Society for Optical Engineering - SPIE, 2003)
From a system level perspective, this paper presents a 128 × 128 flexible and reconfigurable Focal-Plane Analog Programmable Array Processor, which has been designed as a single chip in a 0.35μm standard digital 1P-5M CMOS ...
Ponencia
Structure reconfigurability of the CNNUC3 for robust template operation
(Institute of Electrical and Electronics Engineers, 2000)
We demonstrate the importance of the reconfigurability of a 64/spl times/64 cells size CNN-UM chip. As we show, in such a high complexity mixed-signal VLSI circuit the switch and internal reference level reconfigurability ...
Artículo
A 1000 FPS at 128×128 vision processor with 8-bit digitized I/O
(Institute of Electrical and Electronics Engineers, 2004)
This paper presents a mixed-signal programmable chip for high-speed vision applications. It consists of an array of processing elements, arranged to operate in accordance with the principles of single instruction multiple ...
Ponencia
Analog weight buffering strategy for CNN chips
(Institute of Electrical and Electronics Engineers, 2003)
Large, gray-scale CNN chips employ analog signals to achieve high-density in the internal distribution of the template parameters. Despite the design strategies adopted at the circuitry employed to implement the weights, ...
Artículo
SIRENA: A CAD environment for behavioural modelling and simulation of VLSI cellular neural network chips
(Wiley-Blackwell, 1999)
This paper presents SIRENA, a CAD environment for the simulation and modelling of mixed-signal VLSI parallel processing chips based on cellular neural networks. SIRENA includes capabilities for: (a) the description of ...
Ponencia
Object oriented image segmentation on the CNNUC3 chip
(Institute of Electrical and Electronics Engineers, 2000)
We show how a complex object oriented image analysis algorithm can be implemented on a CNNUM chip for video-coding. Besides the applied linear operations, several gray-scale nonlinear template operations are also emulated ...
Ponencia
A versatile sensor interface for programmable vision systems-on-chip
(The International Society for Optical Engineering - SPIE, 2003)
This paper describes an optical sensor interface designed for a programmable mixed-signal vision chip. This chip has been designed and manufactured in a standard 0.35μm n-well CMOS technology with one poly layer and five ...
Ponencia
ACE 16k based stand-alone system for real-time pre-processing tasks
(The International Society for Optical Engineering - SPIE, 2005)
This paper describes the design of a programmable stand-alone system for real time vision pre-processing tasks. The system's architecture has been implemented and tested using an ACE16k chip and a Xilinx xc4028xl FPGA. The ...
Ponencia
Experimental demonstration of real-time image-processing using a VLSI analog programmable array processor
(SPIE- The International Society for Optical Engineering, 2000)
This paper describes a full-custom mixed-signal chip which embeds distributed optical signal acquisition, digitallyprogrammable analog parallel processing, and distributed image memory —cache— on a common silicon substrate. ...
Ponencia
Implementation of non-linear templates using a decomposition technique by a 0.5 /spl mu/m CMOS CNN universal chip
(Institute of Electrical and Electronics Engineers, 2000)
This paper demonstrates the processing capabilities of a recently designed analog programmable array processor. This new prototype, called CNNUC3, follows the cellular neural network universal machine computing paradigm. ...