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Artículo
A 0.8-μm CMOS two-dimensional programmable mixed-signal focal-plane array processor with on-chip binary imaging and instructions storage
(Institute of Electrical and Electronics Engineers, 1997)
This paper presents a CMOS chip for the parallel acquisition and concurrent analog processing of two-dimensional (2-D) binary images. Its processing function is determined by a reduced set of 19 analog coefficients whose ...
Ponencia
CMOS Architectures and circuits for high-speed decision-making from image flows
(The International Society for Optical Engineering (SPIE), 2008)
We present architectures, CMOS circuits and CMOS chips to process image flows at very high speed. This is achieved by exploiting bio-inspiration and performing processing tasks in parallel manner and concurrently with image ...