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Browsing by Author "Avedillo de Juan, María José"
Now showing items 1-20 of 35
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Article
A practical floating-gate Muller-C element using vMOS threshold gates
Rodríguez Villegas, Esther; Huertas Sánchez, Gloria; Avedillo de Juan, María José; Quintana Toledo, José María; Rueda Rueda, Adoración (Institute of Electrical and Electronics Engineers, 2001)This paper presents the rationale for vMOS-based realizations of digital circuits when logic design techniques based on ...
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PhD Thesis
Algoritmos de codificación binaria de símbolos para la síntesis lógica de circuitos integrados digitales
Martínez Pérez, Manuel (2003-03-30) -
PhD Thesis
Una aproximación al diseño óptimo de máquinas de estados finitos
Avedillo de Juan, María José (1992-01-01)En los Capítulos 2 y 3 se aborda el diseño lógico FSMs. En el primero de ellos estudiamos el problema de la reducción del ...
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Presentation
Assessing application areas for tunnel transistor technologies
Avedillo de Juan, María José; Nuñez Martínez, Juan (Institute of Electrical and Electronics Engineers (IEEE), 2016)Tunnel transistors are one of the most attractive steep subthreshold slope devices currently being investigated as a means ...
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Presentation
Bifurcation Diagrams in MOS-NDR Frequency Divider Circuits
Núñez Martínez, Juan; Avedillo de Juan, María José; Quintana Toledo, José María (Instituto Nacional de Astrofísica, Óptica y Electrónica; Universidad de Sevilla, 2012-03)The behavior of a circuit able to implement frequency division is studied. It is composed of a block with an IV characteristic ...
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Article
Comparative Analysis of Projected Tunnel and CMOS Transistors for Different Logic Application Areas
Nuñez Martínez, Juan; Avedillo de Juan, María José (Institute of Electrical and Electronics Engineers, 2016)In this paper, five projected tunnel FET (TFET) technologies are evaluated and compared with MOSFET and FinFET transistors ...
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Article
Comparison of TFETs and CMOS using optimal design points for power-speed trade-offs
Nuñez Martínez, Juan; Avedillo de Juan, María José (Institute of Electrical and Electronics Engineers, 2017)Tunnel transistors are one of the most attractive steep subthreshold slope devices currently being investigated as a means ...
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Presentation
Complementary tunnel gate topology to reduce crosstalk effects
Nuñez Martínez, Juan; Avedillo de Juan, María José (Institute of Electrical and Electronics Engineers (IEEE), 2017)Tunnel transistors are one of the most attractive steep subthreshold slope devices which are being investigated to overcome ...
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Article
COPAS: A New Algorithm for the Partial Input Encoding Problem
Martínez, Manuel; Avedillo de Juan, María José; Quintana Toledo, José María; Huertas Díaz, José Luis (Hindawi Publishing Corporation, 2002)Frequently, the logic designer deals with functions with symbolic input variables. The binary encoding of such symbols ...
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PhD Thesis
Desarrollo y evaluación de arquitecturas lógicas basadas en Nanopipeline.
Quintero Álvarez, Héctor Javier (2018-07-17)El potencial de la lógica dinámica, con sus fases de precarga y evaluación es una solución muy estudiada y aplicada, para ...
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Master's Final Project
Diseño de sistemas empotrados para aplicaciones de procesado de imagen y vídeo sobre FPGAs usando Vivado SDSoC
Pino Roldán, Roberto Joaquín del (2019-09)El procesado de imagen y vídeo es un campo que tiene una amplia área de aplicaciones, abarcando desde la automatización ...
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PhD Thesis
Diseño lógico de circuitos digitales usando dispositivos con característica NDR
Núñez Martínez, Juan (2011-02-04)En esta tesis doctoral se han desarrollado técnicas de diseño para circuitos electrónicos integrados que empleen dispositivos ...
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Presentation
DOE based high-performance gate-level pipelines
Nuñez Martínez, Juan; Avedillo de Juan, María José; Quintero Álvarez, Héctor Javier (Institute of Electrical and Electronics Engineers, 2014)Domino dynamic circuits are widely used in critical parts of high performance systems. In this paper we show that in ...
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Article
Domino inspired MOBILE networks
Nuñez Martínez, Juan; Avedillo de Juan, María José; Quintana Toledo, José María (Institute of Electrical and Electronics Engineers, 2012)MOBILE networks can be operated in a gate-level pipelined fashion allowing high through-output. If MOBILE gates are directly ...
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Article
Efficient realization of a threshold voter for self-purging redundancy
Quintana Toledo, José María; Avedillo de Juan, María José; Huertas Díaz, José Luis (Springer, 2001)The self-purging technique is not commonly used mainly due to the lack of practical implementations of its key component, ...
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Article
Efficient state reduction methods for PLA-based sequential circuits
Avedillo de Juan, María José; Quintana Toledo, José María; Huertas Díaz, José Luis (Institute of Electrical and Electronics Engineers, 1992)Experiences with heuristics for the state reduction of finite-state machines are presented and two new heuristic algorithms ...
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Article
Experimental Validation of a Two-Phase Clock Scheme for Fine-Grained Pipelined Circuits Based on Monostable to Bistable Logic Elements
Nuñez Martínez, Juan; Avedillo de Juan, María José; Quintana Toledo, José María (Institute of Electrical and Electronics Engineers, 2014)Abstract: Research on fine-grained pipelines can be a way to obtain high-performance applications. Monostable to bistable ...
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Presentation
Exploring logic architectures suitable for TFETs devices
Nuñez Martínez, Juan; Avedillo de Juan, María José (Institute of Electrical and Electronics Engineers, 2017)Tunnel transistors are steep subthreshold slope devices suitable for low voltage operation so being potential candidates ...
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Article
Hardware Implementation of Differential Oscillatory Neural Networks Using VO 2-Based Oscillators and Memristor-Bridge Circuits
Shamsi, Jafar; Avedillo de Juan, María José; Linares Barranco, Bernabé; Serrano Gotarredona, María Teresa (Frontiers Media, 2021)Oscillatory Neural Networks (ONNs) are currently arousing interest in the research community for their potential to implement ...
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Presentation
Holding Dissapearance in RTD-based Quantizers
Nuñez Martínez, Juan; Quintana Toledo, José María; Avedillo de Juan, María José (Laboratoire TIMA, 2007)Multiple-valued Logic (MVL) circuits are one of the most attractive applications of the Monostable-to-Multistable transition ...