Browsing by Author "Avedillo de Juan, María José"
Now showing items 1-20 of 46
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Article
A practical floating-gate Muller-C element using vMOS threshold gates
(Institute of Electrical and Electronics Engineers, 2001)This paper presents the rationale for vMOS-based realizations of digital circuits when logic design techniques based on ...
- PhD Thesis
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PhD Thesis
Una aproximación al diseño óptimo de máquinas de estados finitos
(1992-01-01)En los Capítulos 2 y 3 se aborda el diseño lógico FSMs. En el primero de ellos estudiamos el problema de la reducción del ...
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Presentation
Assessing application areas for tunnel transistor technologies
(Institute of Electrical and Electronics Engineers (IEEE), 2016)Tunnel transistors are one of the most attractive steep subthreshold slope devices currently being investigated as a means ...
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Presentation
Bifurcation Diagrams in MOS-NDR Frequency Divider Circuits
(Instituto Nacional de Astrofísica, Óptica y Electrónica; Universidad de Sevilla, 2012-03)The behavior of a circuit able to implement frequency division is studied. It is composed of a block with an IV characteristic ...
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Article
Comparative Analysis of Projected Tunnel and CMOS Transistors for Different Logic Application Areas
(Institute of Electrical and Electronics Engineers, 2016)In this paper, five projected tunnel FET (TFET) technologies are evaluated and compared with MOSFET and FinFET transistors ...
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Article
Comparison of TFETs and CMOS using optimal design points for power-speed trade-offs
(Institute of Electrical and Electronics Engineers, 2017)Tunnel transistors are one of the most attractive steep subthreshold slope devices currently being investigated as a means ...
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Presentation
Complementary tunnel gate topology to reduce crosstalk effects
(Institute of Electrical and Electronics Engineers (IEEE), 2017)Tunnel transistors are one of the most attractive steep subthreshold slope devices which are being investigated to overcome ...
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Article
COPAS: A New Algorithm for the Partial Input Encoding Problem
(Hindawi Publishing Corporation, 2002)Frequently, the logic designer deals with functions with symbolic input variables. The binary encoding of such symbols ...
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PhD Thesis
Desarrollo y evaluación de arquitecturas lógicas basadas en Nanopipeline.
(2018-07-17)El potencial de la lógica dinámica, con sus fases de precarga y evaluación es una solución muy estudiada y aplicada, para ...
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Article
Digital Implementation of Oscillatory Neural Network for Image Recognition Applications
(Frontiers Media, 2021)Computing paradigm based on von Neuman architectures cannot keep up with the ever-increasing data growth (also called “data ...
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Master's Final Project
Diseño de sistemas empotrados para aplicaciones de procesado de imagen y vídeo sobre FPGAs usando Vivado SDSoC
(2019-09)El procesado de imagen y vídeo es un campo que tiene una amplia área de aplicaciones, abarcando desde la automatización ...
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PhD Thesis
Diseño lógico de circuitos digitales usando dispositivos con característica NDR
(2011-02-04)En esta tesis doctoral se han desarrollado técnicas de diseño para circuitos electrónicos integrados que empleen dispositivos ...
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Presentation
DOE based high-performance gate-level pipelines
(Institute of Electrical and Electronics Engineers, 2014)Domino dynamic circuits are widely used in critical parts of high performance systems. In this paper we show that in ...
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Article
Domino inspired MOBILE networks
(Institute of Electrical and Electronics Engineers, 2012)MOBILE networks can be operated in a gate-level pipelined fashion allowing high through-output. If MOBILE gates are directly ...
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Article
Effect of Device Mismatches in Differential Oscillatory Neural Networks
(IEEE, 2023-02)Analog implementation of Oscillatory Neural Networks (ONNs) has the potential to implement fast and ultra-low-power computing ...
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Article
Efficient realization of a threshold voter for self-purging redundancy
(Springer, 2001)The self-purging technique is not commonly used mainly due to the lack of practical implementations of its key component, ...
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Presentation
Efficient realization of RTD-CMOS logic gates
(2011)The incorporation of Resonant Tunnel Diodes (RTDs) into III/V transistor technologies has shown an improved circuit ...
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Article
Efficient state reduction methods for PLA-based sequential circuits
(Institute of Electrical and Electronics Engineers, 1992)Experiences with heuristics for the state reduction of finite-state machines are presented and two new heuristic algorithms ...
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Article
Experimental Validation of a Two-Phase Clock Scheme for Fine-Grained Pipelined Circuits Based on Monostable to Bistable Logic Elements
(Institute of Electrical and Electronics Engineers, 2014)Abstract: Research on fine-grained pipelines can be a way to obtain high-performance applications. Monostable to bistable ...