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Browsing by Author "Serrano Gotarredona, Rafael"  

Now showing items 1-12 of 12

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      A neuromorphic cortical-layer microchip for spike-based event processing vision systems 

      Serrano Gotarredona, Rafael; Serrano Gotarredona, María Teresa; Acosta Jiménez, Antonio José; Linares Barranco, Bernabé (Institute of Electrical and Electronics Engineers, 2006)
      We present a neuromorphic cortical-layer processing microchip for address event representation (AER) spike-based processing ...
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      A spatial contrast retina with on-chip calibration for neuromorphic spike-based AER vision systems 

      Costas Santos, Jesús; Serrano Gotarredona, María Teresa; Serrano Gotarredona, Rafael; Linares Barranco, Bernabé (Institute of Electrical and Electronics Engineers, 2007)
      We present a 32 32 pixels contrast retina microchip that provides its output as an address event representation (AER) ...
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      AER Building Blocks for Multi-Layer Multi-Chip Neuromorphic Vision Systems 

      Serrano Gotarredona, Rafael; Oster, M.; Lichtsteiner, P.; Linares Barranco, Alejandro; Paz Vicente, Rafael; Gómez Rodríguez, Francisco de Asís; Kolle Riis, H.; Delbrück, Tobi; Liu, Shih-Chii; Zahnd, S.; Whatley, A.M.; Douglas, R.; Häfliger, P.; Jiménez Moreno, Gabriel; Civit Balcells, Antón; Serrano Gotarredona, María Teresa; Acosta Jiménez, Antonio José; Linares Barranco, Bernabé (Neural Information Processing Systems Foundation, 2005)
      A 5-layer neuromorphic vision processor whose components communicate spike events asychronously using the ...
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      An AER Contrast Retina with On-Chip Calibration 

      Costas Santos, Jesús; Serrano Gotarredona, María Teresa; Serrano Gotarredona, Rafael; Linares Barranco, Bernabé (IEEE Computer Society, 2007)
      We present a contrast retina microchip that provides its output as an AER (Address Event Representation) stream. Contrast ...
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      CAVIAR: A 45k neuron, 5M synapse, 12G connects/s AER hardware sensory-processing-learning-actuating system for high-speed visual object recognition and tracking 

      Serrano Gotarredona, Rafael; Oster, Matthias; Lichtsteiner, Patrick; Linares Barranco, Alejandro; Paz Vicente, Rafael; Gómez Rodríguez, Francisco de Asís; Camuñas Mesa, Luis Alejandro; Berner, Raphael; Rivas Pérez, Manuel; Jiménez Moreno, Gabriel; Civit Balcells, Antón; Serrano Gotarredona, María Teresa; Acosta Jiménez, Antonio José; Linares Barranco, Bernabé (Institute of Electrical and Electronics Engineers, 2009)
      This paper describes CAVIAR, a massively parallel hardware implementation of a spike-based sensing-processing-learning-actuating ...
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      Compact low-power calibration mini-DACs for neural arrays with programmable weights 

      Linares Barranco, Bernabé; Serrano Gotarredona, María Teresa; Serrano Gotarredona, Rafael (Institute of Electrical and Electronics Engineers, 2003)
      This paper considers the viability of compact low-resolution low-power mini digital-to-analog converters (mini-DACs) for ...
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      High-speed image processing with AER-based components 

      Serrano Gotarredona, Rafael; Linares Barranco, Bernabé; Serrano Gotarredona, María Teresa; Acosta Jiménez, Antonio José; Linares Barranco, Alejandro; Paz Vicente, Rafael; Gómez Rodríguez, Francisco de Asís; Jiménez Moreno, Gabriel; Civit Balcells, Antón (IEEE Computer Society, 2006)
      A high speed sample image processing application using AER-based components is presented. The setup objective is to ...
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      LVDS interface for AER links with burst mode operation capability 

      Zamarreño Ramos, Carlos; Serrano Gotarredona, Rafael; Serrano Gotarredona, María Teresa; Linares Barranco, Bernabé (IEEE Computer Society, 2008)
      This paper presents the design and simulation of a serial AER LVDS communication link. It converts data from classical ...
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      LVDS Serial AER Link performance 

      Miró Amarante, María Lourdes; Jiménez Fernández, Ángel Francisco; Linares Barranco, Alejandro; Gómez Rodríguez, Francisco de Asís; Paz Vicente, Rafael; Jiménez Moreno, Gabriel; Civit Balcells, Antón; Serrano Gotarredona, Rafael (IEEE Computer Society, 2007)
      Address-Event-Representation (AER) is a communication protocol for transferring asynchronous events between VLSI chips, ...
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      On Real-Time AER 2-D Convolutions Hardware for Neuromorphic Spike-Based Cortical Processing 

      Serrano Gotarredona, Rafael; Serrano Gotarredona, María Teresa; Acosta Jiménez, Antonio José; Serrano Gotarredona, Clara; Pérez Carrasco, José Antonio; Linares Barranco, Bernabé; Linares Barranco, Alejandro; Jiménez Moreno, Gabriel; Civit Balcells, Antón (IEEE Computer Society, 2008)
      In this paper, a chip that performs real-time image convolutions with programmable kernels of arbitrary shape is ...
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      Spike Events Processing for Vision Systems 

      Serrano Gotarredona, Rafael; Serrano Gotarredona, María Teresa; Acosta Jiménez, Antonio José; Linares Barranco, Alejandro; Jiménez Moreno, Gabriel; Civit Balcells, Antón; Linares Barranco, Bernabé (IEEE Computer Society, 2007)
      In this paper we briefly summarize the fundamental properties of spike events processing applied to artificial vision ...
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      The stochastic I-Pot: A circuit block for programming bias currents 

      Serrano Gotarredona, Rafael; Camuñas Mesa, Luis Alejandro; Serrano Gotarredona, María Teresa; Leñero Bardallo, Juan Antonio; Linares Barranco, Bernabé (Institute of Electrical and Electronics Engineers, 2007)
      In this brief, we present the “Stochastic I-Pot.” It is a circuit element that allows for digitally programming a precise ...