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Listar por autor "Mir, Salvador"
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Ponencia
On-chip Reduced-code Static Linearity Test of Vcm-based Switching SAR ADCs Using an Incremental Analog-to-digital Converter
Feitoza, Renato S.; Barragan, Manuel J.; Ginés Arteaga, Antonio José; Mir, Salvador (Institute of Electrical and Electronics Engineers (IEEE), 2020)This paper describes a BIST technique for the static linearity test of Vcm-based successive-approximation analog-to-digital ...
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Ponencia
Static Linearity BIST for Vcm-based Switching SAR ADCs Using a Reduced-code Measurement Technique
Feitoza, Renato S.; Barragan, Manuel J.; Ginés Arteaga, Antonio José; Mir, Salvador (Institute of Electrical and Electronics Engineers (IEEE), 2020)This work presents a reduced-code strategy for the static linearity self-testing of Vcm -based successive-approximation ...