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Now showing items 253-272 of 107767
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Article
A toponímia proto-histórica como ferramenta do arqueólogo? Comentários sobre uma relação problemática
(Universidad Complutense de Madrid : Servicio de Publicaciones, 2018)Estudos recentes têm vindo a destacar a toponímia proto-histórica enquanto ferramenta para a interpretação do registo ...
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Presentation
A 0.13μm CMOS current steering D/A converter for PLC and VDSL applications
(2005)This paper describes the design of a 12-bit 80MS/s Digital-to-Analog converter implemented in a 0.13μm CMOS logic ...
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Presentation
A 0.18 μm CMOS low noise, highly linear continuous-time seventh-order elliptic low-pass filter
(The International Society for Optical Engineering- SPIE, 2005)This paper presents a fast procedure for the system-level evaluation of noise and distortion in continuous-time integrated ...
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Presentation
A 0.18μm CMOS low-noise elliptic low-pass continuous-time filter
(Institute of Electrical and Electronics Engineers, 2005)This paper presents a seventh order low-pass continuous-time elliptic filter for use in a high-performance wireline ...
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Presentation
A 0.35 μm CMOS 17-bit@40-kS/s cascade 2-1 ΣΔ modulator with programmable gain and programmable chopper stabilization
(The International Society for Optical Engineering - SPIE, 2005)This paper describes a 0.35μm CMOS chopper-stabilized Switched-Capacitor 2-1 cascade ΣDelta; modulator for automotive ...
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Presentation
A 0.35μm CMOS 17-bit@40kS/s Sensor A/D Interface Based on a Programmable-Gain Cascade 2-1 ΣΔ Modulator
(Institute of Electrical and Electronics Engineers, 2004)This paper describes the design and electrical implementation of an A/D interface for sensor applications realized in a ...
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Presentation
A 0.5 /spl mu/m CMOS CNN analog random access memory chip for massive image processing
(Institute of Electrical and Electronics Engineers, 1998)An analog RAM has been designed to act as a cache memory for a CNN Universal Machine. Hence, all the non-standard chips ...
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Article
A 0.8-μm CMOS two-dimensional programmable mixed-signal focal-plane array processor with on-chip binary imaging and instructions storage
(Institute of Electrical and Electronics Engineers, 1997)This paper presents a CMOS chip for the parallel acquisition and concurrent analog processing of two-dimensional (2-D) ...
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Presentation
A 1.25V FGMOS Filter Using Translinear Circuits
(IEEE Computer Society, 2001)This paper presents a new low voltage/low power filter design based on Floating-Gate MOS (FGMOS) transistors. FGMOS ...
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Article
A 1.5 ns OFF/ON Switching-Time Voltage-Mode LVDS Driver/Receiver Pair for Asynchronous AER Bit-Serial Chip Grid Links With Up to 40 Times Event-Rate Dependent Power Savings
(IEEE Computer Society, 2013)This paper presents a low power fast ON/OFF switchable voltage mode implementation of a driver/receiver pair intended ...
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Article
A 1000 FPS at 128×128 vision processor with 8-bit digitized I/O
(Institute of Electrical and Electronics Engineers, 2004)This paper presents a mixed-signal programmable chip for high-speed vision applications. It consists of an array of ...
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Presentation
A 12-bit@40MS/s Gm-C Cascade 3-2 Continuous-Time Sigma-Delta Modulator
(Institute of Electrical and Electronics Engineers, 2007)This paper reports the transistor-level design of a 130-nm CMOS continuous-time cascade ΣΔ modulator. The modulator topology, ...
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Article
A 13-bit, 2.2-MS/s, 55-mW multibit cascade ΣΔ modulator in CMOS 0.7-μm single-poly technology
(Institute of Electrical and Electronics Engineers, 1999)This paper presents a CMOS 0.7-μm ΣΔ modulator IC that achieves 13-bit dynamic range at 2.2 MS/s with an oversampling ratio ...
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Presentation
A 14-bit 4-MS/s Multi-bit Cascade Sigma-Delta Modulator in CMOS 0.35-um Digital Technology
(2000)This paper presents a 4th-order 3-stage cascade SD modulator that achieves 14-bit dynamic range at 4MS/s using low ...
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Presentation
A 148dB focal-plane tone-mapping QCIF imager
(Institute of Electrical and Electronics Engineers, 2012)This paper presents a QCIF HDR imager where visual information is simultaneously captured and adaptively compressed by an ...
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Article
A 151 dB high dynamic range CMOS image sensor chip architecture with tone mapping compression embedded in-pixel
(Institute of Electrical and Electronics Engineers, 2015)This paper presents a high dynamic range CMOS image sensor that implements an in-pixel content-aware adaptive global tone ...
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Presentation
A 16 Rules@2.5Mflips Mixed-Signal Programmable Fuzzy Controller CMOS-1μm Chip
(Institute of Electrical and Electronics Engineers, 1996)We present a fuzzy inference chip capable to evaluate 16 programmable rules at a speed of 2.5Mflips (2.5 × 10 6 fuzzy ...
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Presentation
A 176x144 148dB adaptive tone-mapping imager
(Society of Photo-Optical Instrumentation Engineers, 2012)This paper presents a 176x144 (QCIF) HDR image sensor where visual information is simultaneously captured and adaptively ...