Artículo
1 V CMOS subthreshold log domain PDM
Autor/es | Serra Graells, Francesc
Huertas Díaz, José Luis |
Fecha de publicación | 2003 |
Fecha de depósito | 2018-07-12 |
Publicado en |
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Resumen | A new CMOS circuit strategy for very low-voltage Pulse-Duration Modulators (PDM) is proposed. Optimization of voltage supply scaling below the sum of threshold voltages is based on Instantaneous Log Companding processing ... A new CMOS circuit strategy for very low-voltage Pulse-Duration Modulators (PDM) is proposed. Optimization of voltage supply scaling below the sum of threshold voltages is based on Instantaneous Log Companding processing through the MOSFET operating in weak inversion. A 1 V VLSI PDM circuit for very low-voltage audio applications such as Hearing Aids is presented, showing good agreement between simulated and experimental data. |
Agencias financiadoras | Comisión Interministerial de Ciencia y Tecnología (CICYT). España European Union (UE) |
Identificador del proyecto | TIC97-1159
TIC99-1084 23068 |
Cita | Serra Graells, F. y Huertas Díaz, J.L. (2003). 1 V CMOS subthreshold log domain PDM. Analog Integrated Circuits and Signal Processing, 34 (3), 183-187. |
Ficheros | Tamaño | Formato | Ver | Descripción |
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1V CMOS Subthreshold.pdf | 277.4Kb | [PDF] | Ver/ | |