Artículo
Background Digital Calibration of Comparator Offsets in Pipeline ADCs
Autor/es | Ginés Arteaga, Antonio José
Peralías Macías, Eduardo Rueda Rueda, Adoración |
Fecha de publicación | 2015 |
Fecha de depósito | 2017-09-20 |
Publicado en |
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Resumen | This brief presents a low-cost digital technique for background calibration of comparator offsets in pipeline analog-to-digital converters (ADCs). Thanks to calibration, comparator offset errors above half the stage ... This brief presents a low-cost digital technique for background calibration of comparator offsets in pipeline analog-to-digital converters (ADCs). Thanks to calibration, comparator offset errors above half the stage least-significant bit margin in a unitary redundancy scheme are admissible, thus relaxing comparator design requirements and allowing their optimization for low-power high-speed applications and low input capacitance. The technique also makes it possible to relax design requirements of stage amplifiers within the pipeline queue, since output swing and driving capability are significantly lower. In this brief, the proposal is validated using realistic hardware-behavioral models. |
Agencias financiadoras | Junta de Andalucía Gobierno de España |
Identificador del proyecto | P09-TIC-5386
TEC2011-28302 |
Cita | Ginés Arteaga, A.J., Peralias Macias, E. y Rueda Rueda, A. (2015). Background Digital Calibration of Comparator Offsets in Pipeline ADCs. IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 99-. |
Ficheros | Tamaño | Formato | Ver | Descripción |
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Background Digital Calibration.pdf | 436.0Kb | [PDF] | Ver/ | |