Presentation
Gate-Level Simulation of CMOS Circuits Using the IDDM Model
Author/s | Bellido Díaz, Manuel Jesús
Juan Chico, Jorge Ruiz de Clavijo Vázquez, Paulino Acosta Jiménez, Antonio José Valencia Barrero, Manuel |
Department | Universidad de Sevilla. Departamento de Tecnología Electrónica Universidad de Sevilla. Departamento de Electrónica y Electromagnetismo |
Publication Date | 2001 |
Deposit Date | 2017-01-19 |
Published in |
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ISBN/ISSN | 0-7803-6685-9 |
Abstract | Timing verification of digital CMOS circuits is a
key point in the design process. In this contribution we present
the extension to gates of the Inertial and Degradation Delay
Model for logic timing simulation which is ... Timing verification of digital CMOS circuits is a key point in the design process. In this contribution we present the extension to gates of the Inertial and Degradation Delay Model for logic timing simulation which is able to take account of the propagation of arbitrarily narrow pulses. As a result, the model is ready to be applied to the simulation and verification of complex circuits. Simulation results show an accuracy similar to HSPICE and greatly improved precision over conventional delay models. |
Funding agencies | Ministerio de Ciencia y Tecnología (MCYT). España |
Project ID. | TIC 2000-1350 |
Citation | Bellido Díaz, M.J., Juan Chico, J., Ruiz de Clavijo Vázquez, P., Acosta Jiménez, A.J. y Valencia Barrero, M. (2001). Gate-Level Simulation of CMOS Circuits Using the IDDM Model. En ISCAS 2001. The 2001 IEEE International Symposium on Circuits and Systems (483-486), Sidney, Australia: IEEE Computer Society. |
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Gate-Level.pdf | 382.9Kb | [PDF] | View/ | |