Capítulo de Libro
Influence of Clocking Strategies on the Design of Low Switching-Noise Digital and Mixed-Signal VLSI Circuits
Autor/es | Acosta Jiménez, Antonio José
Jiménez, R. Juan Chico, Jorge Bellido Díaz, Manuel Jesús Valencia Barrero, Manuel |
Departamento | Universidad de Sevilla. Departamento de Tecnología Electrónica Universidad de Sevilla. Departamento de Electrónica y Electromagnetismo |
Fecha de publicación | 2000 |
Fecha de depósito | 2017-01-18 |
Publicado en |
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ISBN/ISSN | 978-3-540-41068-3 0302-9743 |
Resumen | This communication shows the influence of clocking schemes on the
digital switching noise generation. It will be shown how the choice of a suited
clocking scheme for the digital part reduces the switching noise, thus ... This communication shows the influence of clocking schemes on the digital switching noise generation. It will be shown how the choice of a suited clocking scheme for the digital part reduces the switching noise, thus alleviating the problematic associated to limitations of performances in mixed-signal Analog/Digital Integrated Circuits. Simulation data of a pipelined XOR chain using both a single-phase and a two-phase clocking schemes, as well as of two nbit counters with different clocking styles lead, as conclusions, to recommend multiple clock-phase and asynchronous styles for reducing switching noise. |
Cita | Acosta Jiménez, A.J., Jiménez, R.,...,Valencia Barrero, M. (2000). Influence of Clocking Strategies on the Design of Low Switching-Noise Digital and Mixed-Signal VLSI Circuits. En Integrated Circuit Design. PATMOS 2000. Lecture Notes in Computer Science, vol 1918. (pp. 316-326). Berlin: Springer. |
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