Live demonstration: Hardware implementation of convolutional STDP for on-line visual feature learning

Yousefzadeh, Amirreza; Masquelier, T.; Serrano Gotarredona, María Teresa; Linares Barranco, Bernabé

doi:10.1109/ISCAS.2017.8050395

Ponencia

dc.creator	Yousefzadeh, Amirreza	es
dc.creator	Masquelier, T.	es
dc.creator	Serrano Gotarredona, María Teresa	es
dc.creator	Linares Barranco, Bernabé	es
dc.date.accessioned	2020-07-08T12:05:04Z
dc.date.available	2020-07-08T12:05:04Z
dc.date.issued	2017
dc.identifier.citation	Yousefzadeh, A., Masquelier, T., Serrano Gotarredona, M.T. y Linares Barranco, B. (2017). Live demonstration: Hardware implementation of convolutional STDP for on-line visual feature learning. En 2017ISCAS. IEEE International Symposium on Circuits and Systems Baltimore (USA): IEEE. Institute of Electrical and Electronics Engineers.
dc.identifier.issn	2379-447X	es
dc.identifier.uri	https://hdl.handle.net/11441/99046
dc.description.abstract	We present live demonstration of a hardware that can learn visual features on-line and in real-time during presentation of objects. Input Spikes are coming from a bio-inspired silicon retina or Dynamic Vision Sensor (DVS) and are processed in a Spiking Convolutional Neural Network (SCNN) that is equipped with a Spike Timing Dependent Plasticity (STDP) learning rule implemented on FPGA.	es
dc.format	application/pdf	es
dc.format.extent	1 p.	es
dc.language.iso	eng	es
dc.publisher	IEEE. Institute of Electrical and Electronics Engineers	es
dc.relation.ispartof	2017ISCAS. IEEE International Symposium on Circuits and Systems (2017),
dc.rights	Attribution-NonCommercial-NoDerivatives 4.0 Internacional	*
dc.rights.uri	http://creativecommons.org/licenses/by-nc-nd/4.0/	*
dc.subject	Visualization	es
dc.subject	Hardware	es
dc.subject	Voltage control	es
dc.subject	Feature extraction	es
dc.subject	Kernel	es
dc.subject	Sociology	es
dc.subject	Statistics	es
dc.title	Live demonstration: Hardware implementation of convolutional STDP for on-line visual feature learning	es
dc.type	info:eu-repo/semantics/conferenceObject	es
dc.type.version	info:eu-repo/semantics/acceptedVersion	es
dc.rights.accessRights	info:eu-repo/semantics/openAccess	es
dc.contributor.affiliation	Universidad de Sevilla. Departamento de Arquitectura y Tecnología de Computadores	es
dc.relation.publisherversion	https://ieeexplore.ieee.org/document/8050395	es
dc.identifier.doi	10.1109/ISCAS.2017.8050395	es
dc.contributor.group	Universidad de Sevilla. TIC178: Diseño y Test de Circuitos Integrados de Señal Mixta	es
idus.validador.nota	Postprint	es
dc.eventtitle	2017ISCAS. IEEE International Symposium on Circuits and Systems	es
dc.eventinstitution	Baltimore (USA)	es

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