dc.creator | Yousefzadeh, Amirreza | es |
dc.creator | Soto, Miguel | es |
dc.creator | Serrano Gotarredona, María Teresa | es |
dc.creator | Galluppi, Francesco | es |
dc.creator | Plana, Luis A. | es |
dc.creator | Furber, Steve B. | es |
dc.creator | Linares Barranco, Bernabé | es |
dc.date.accessioned | 2020-07-08T07:57:08Z | |
dc.date.available | 2020-07-08T07:57:08Z | |
dc.date.issued | 2018 | |
dc.identifier.citation | Yousefzadeh, A., Soto, M., Serrano Gotarredona, M.T., Galluppi, F., Plana, L.A., Furber, S.B. y Linares Barranco, B. (2018). Performance Comparison of Time-Step-Driven versus Event-Driven Neural State Update Approaches in SpiNNaker. En ISCAS2018. IEEE International Symposium on Circuits and Systems (1-4), Florence (Italy): IEEE. Institute of Electrical and Electronics Engineers. | |
dc.identifier.issn | 2379-447X | es |
dc.identifier.uri | https://hdl.handle.net/11441/98974 | |
dc.description.abstract | The SpiNNaker chip is a multi-core processor optimized for neuromorphic applications. Many SpiNNaker chips are assembled to make a highly parallel million core platform. This system can be used for simulation of a large number of neurons in real-time. SpiNNaker is using a general purpose ARM processor that gives a high amount of flexibility to implement different methods for processing spikes. Various libraries and packages are provided to translate a high-level description of Spiking Neural Networks (SNN) to low-level machine language that can be used in the ARM processors. In this paper, we introduce and compare three different methods to implement this intermediate layer of abstraction. We have examined the advantages of each method by various criteria, which can be useful for professional users to choose between them. All the codes that are used in this paper are available for academic propose. | es |
dc.description.sponsorship | EU H2020 grant 644096 ECOMODE | es |
dc.description.sponsorship | EU H2020 grant 687299 NEURAM3 | es |
dc.description.sponsorship | Ministry of Economy and Competitivity (Spain) / European Regional Development Fund TEC2015-63884-C2-1-P (COGNET) | es |
dc.format | application/pdf | es |
dc.format.extent | 4 p. | es |
dc.language.iso | eng | es |
dc.publisher | IEEE. Institute of Electrical and Electronics Engineers | es |
dc.relation.ispartof | ISCAS2018. IEEE International Symposium on Circuits and Systems (2018), pp. 1-4. | |
dc.rights | Attribution-NonCommercial-NoDerivatives 4.0 Internacional | * |
dc.rights.uri | http://creativecommons.org/licenses/by-nc-nd/4.0/ | * |
dc.subject | Neurons | es |
dc.subject | Biological neural networks | es |
dc.subject | Real-time systems | es |
dc.subject | Libraries | es |
dc.subject | Neuromorphics | es |
dc.subject | Multicore processing | es |
dc.title | Performance Comparison of Time-Step-Driven versus Event-Driven Neural State Update Approaches in SpiNNaker | es |
dc.type | info:eu-repo/semantics/conferenceObject | es |
dcterms.identifier | https://ror.org/03yxnpp24 | |
dc.type.version | info:eu-repo/semantics/acceptedVersion | es |
dc.rights.accessRights | info:eu-repo/semantics/openAccess | es |
dc.contributor.affiliation | Universidad de Sevilla. Departamento de Arquitectura y Tecnología de Computadores | es |
dc.relation.projectID | 644096 ECOMODE | es |
dc.relation.projectID | 687299 NEURAM3 | es |
dc.relation.projectID | TEC2015-63884-C2-1-P (COGNET) | es |
dc.relation.publisherversion | https://ieeexplore.ieee.org/document/8350990 | es |
dc.identifier.doi | 10.1109/ISCAS.2018.8350990 | es |
dc.contributor.group | Universidad de Sevilla. TIC178: Diseño y Test de Circuitos Integrados de Señal Mixta | es |
idus.validador.nota | Postprint | es |
dc.publication.initialPage | 1 | es |
dc.publication.endPage | 4 | es |
dc.eventtitle | ISCAS2018. IEEE International Symposium on Circuits and Systems | es |
dc.eventinstitution | Florence (Italy) | es |