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dc.creatorYousefzadeh, Amirrezaes
dc.creatorSoto, Migueles
dc.creatorSerrano Gotarredona, María Teresaes
dc.creatorGalluppi, Francescoes
dc.creatorPlana, Luis A.es
dc.creatorFurber, Steve B.es
dc.creatorLinares Barranco, Bernabées
dc.date.accessioned2020-07-08T07:57:08Z
dc.date.available2020-07-08T07:57:08Z
dc.date.issued2018
dc.identifier.citationYousefzadeh, A., Soto, M., Serrano Gotarredona, M.T., Galluppi, F., Plana, L.A., Furber, S.B. y Linares Barranco, B. (2018). Performance Comparison of Time-Step-Driven versus Event-Driven Neural State Update Approaches in SpiNNaker. En ISCAS2018. IEEE International Symposium on Circuits and Systems (1-4), Florence (Italy): IEEE. Institute of Electrical and Electronics Engineers.
dc.identifier.issn2379-447Xes
dc.identifier.urihttps://hdl.handle.net/11441/98974
dc.description.abstractThe SpiNNaker chip is a multi-core processor optimized for neuromorphic applications. Many SpiNNaker chips are assembled to make a highly parallel million core platform. This system can be used for simulation of a large number of neurons in real-time. SpiNNaker is using a general purpose ARM processor that gives a high amount of flexibility to implement different methods for processing spikes. Various libraries and packages are provided to translate a high-level description of Spiking Neural Networks (SNN) to low-level machine language that can be used in the ARM processors. In this paper, we introduce and compare three different methods to implement this intermediate layer of abstraction. We have examined the advantages of each method by various criteria, which can be useful for professional users to choose between them. All the codes that are used in this paper are available for academic propose.es
dc.description.sponsorshipEU H2020 grant 644096 ECOMODEes
dc.description.sponsorshipEU H2020 grant 687299 NEURAM3es
dc.description.sponsorshipMinistry of Economy and Competitivity (Spain) / European Regional Development Fund TEC2015-63884-C2-1-P (COGNET)es
dc.formatapplication/pdfes
dc.format.extent4 p.es
dc.language.isoenges
dc.publisherIEEE. Institute of Electrical and Electronics Engineerses
dc.relation.ispartofISCAS2018. IEEE International Symposium on Circuits and Systems (2018), pp. 1-4.
dc.rightsAttribution-NonCommercial-NoDerivatives 4.0 Internacional*
dc.rights.urihttp://creativecommons.org/licenses/by-nc-nd/4.0/*
dc.subjectNeuronses
dc.subjectBiological neural networkses
dc.subjectReal-time systemses
dc.subjectLibrarieses
dc.subjectNeuromorphicses
dc.subjectMulticore processinges
dc.titlePerformance Comparison of Time-Step-Driven versus Event-Driven Neural State Update Approaches in SpiNNakeres
dc.typeinfo:eu-repo/semantics/conferenceObjectes
dcterms.identifierhttps://ror.org/03yxnpp24
dc.type.versioninfo:eu-repo/semantics/acceptedVersiones
dc.rights.accessRightsinfo:eu-repo/semantics/openAccesses
dc.contributor.affiliationUniversidad de Sevilla. Departamento de Arquitectura y Tecnología de Computadoreses
dc.relation.projectID644096 ECOMODEes
dc.relation.projectID687299 NEURAM3es
dc.relation.projectIDTEC2015-63884-C2-1-P (COGNET)es
dc.relation.publisherversionhttps://ieeexplore.ieee.org/document/8350990es
dc.identifier.doi10.1109/ISCAS.2018.8350990es
dc.contributor.groupUniversidad de Sevilla. TIC178: Diseño y Test de Circuitos Integrados de Señal Mixtaes
idus.validador.notaPostprintes
dc.publication.initialPage1es
dc.publication.endPage4es
dc.eventtitleISCAS2018. IEEE International Symposium on Circuits and Systemses
dc.eventinstitutionFlorence (Italy)es

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