dc.contributor.editor | Maloberti, Franco | es |
dc.contributor.editor | Setti, Gianluca | es |
dc.creator | Yousefzadeh, Amirreza | es |
dc.creator | Orchard, Garrick | es |
dc.creator | Stromatias, Evangelos | es |
dc.creator | Serrano Gotarredona, María Teresa | es |
dc.creator | Linares Barranco, Bernabé | es |
dc.date.accessioned | 2020-07-08T07:51:09Z | |
dc.date.available | 2020-07-08T07:51:09Z | |
dc.date.issued | 2018 | |
dc.identifier.citation | Yousefzadeh, A., Orchard, G., Stromatias, E., Serrano Gotarredona, M.T. y Linares Barranco, B. (2018). Hybrid Neural Network, An Efficient Low-Power Digital Hardware Implementation of Event-based Artificial Neural Network. En ISCAS2018. IEEE International Symposium on Circuits and Systems Florence (Italy): Institute of Electrical and Electronics Engineers (IEEE). | |
dc.identifier.issn | 0271-4310 | es |
dc.identifier.issn | 2379-447X | es |
dc.identifier.uri | https://hdl.handle.net/11441/98971 | |
dc.description.abstract | Interest in event-based vision sensors has proliferated
in recent years, with innovative technology becoming more
accessible to new researchers and highlighting such sensors’
potential to enable low-latency sensing at low computational
cost. These sensors can outperform frame-based vision sensors
regarding data compression, dynamic range, temporal resolution
and power efficiency. However, available mature framebased
processing methods by using Artificial Neural Networks
(ANNs) surpass Spiking Neural Networks (SNNs) in terms of
accuracy of recognition. In this paper, we introduce a Hybrid
Neural Network which is an intermediate solution to exploit
advantages of both event-based and frame-based processing.We
have implemented this network in FPGA and benchmarked its
performance by using different event-based versions of MNIST
dataset. HDL codes for this project are available for academic
purpose upon request. | es |
dc.format | application/pdf | es |
dc.format.extent | 15 p. | es |
dc.language.iso | eng | es |
dc.publisher | Institute of Electrical and Electronics Engineers (IEEE) | es |
dc.relation.ispartof | ISCAS2018. IEEE International Symposium on Circuits and Systems (2018). | |
dc.rights | Attribution-NonCommercial-NoDerivatives 4.0 Internacional | * |
dc.rights.uri | http://creativecommons.org/licenses/by-nc-nd/4.0/ | * |
dc.subject | Voltage control | es |
dc.subject | Neurons | es |
dc.subject | Biological neural networks | es |
dc.subject | Field programmable gate arrays | es |
dc.subject | Hardware | es |
dc.subject | Sensors | es |
dc.title | Hybrid Neural Network, An Efficient Low-Power Digital Hardware Implementation of Event-based Artificial Neural Network | es |
dc.type | info:eu-repo/semantics/conferenceObject | es |
dcterms.identifier | https://ror.org/03yxnpp24 | |
dc.type.version | info:eu-repo/semantics/acceptedVersion | es |
dc.rights.accessRights | info:eu-repo/semantics/openAccess | es |
dc.contributor.affiliation | Universidad de Sevilla. Departamento de Arquitectura y Tecnología de Computadores | es |
dc.relation.publisherversion | https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=8351562&isnumber=8350884 | es |
dc.identifier.doi | 10.1109/ISCAS.2018.8351562 | es |
dc.contributor.group | Universidad de Sevilla. TIC178: Diseño y Test de Circuitos Integrados de Señal Mixta | es |
idus.validador.nota | Postprint | es |
dc.eventtitle | ISCAS2018. IEEE International Symposium on Circuits and Systems | es |
dc.eventinstitution | Florence (Italy) | es |