Ponencia
A one-transistor-synapse strategy for electrically-programmable massively-parallel analog array processors
Autor/es | Domínguez Castro, Rafael
Espejo Meana, Servando Carlos Rodríguez Vázquez, Ángel Benito Carmona Galán, Ricardo |
Departamento | Universidad de Sevilla. Departamento de Electrónica y Electromagnetismo |
Fecha de publicación | 1997 |
Fecha de depósito | 2020-04-20 |
Publicado en |
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ISBN/ISSN | 0-7803-4240-2 |
Resumen | This paper presents a linear, four-quadrants, electrically-programmable, one-transistor synapse strategy applicable to the implementation of general massively-parallel analog processors in CMOS technology. It is specially ... This paper presents a linear, four-quadrants, electrically-programmable, one-transistor synapse strategy applicable to the implementation of general massively-parallel analog processors in CMOS technology. It is specially suited for translationally-invariant processing arrays with local connectivity, and results in a significant reduction in area occupation and power dissipation of the basic processing units. This allows higher integration densities and therefore, permits the integration of larger arrays on a single chip. |
Identificador del proyecto | TIC96- 1392-C02-02 |
Cita | Domínguez Castro, R., Espejo Meana, S.C., Rodríguez Vázquez, Á.B. y Carmona Galán, R. (1997). A one-transistor-synapse strategy for electrically-programmable massively-parallel analog array processors. En 2nd IEEE-CAS Region 8 Workshop on Analog and Mixed IC Design (117-122), Baveno, Italia: Institute of Electrical and Electronics Engineers. |
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