Artículo
Analog Neural Programmable Optimizers in CMOS VLSI Technologies
Autor/es | Domínguez Castro, Rafael
Rodríguez Vázquez, Ángel Benito Huertas Díaz, José Luis Sánchez Sinencio, Edgar |
Departamento | Universidad de Sevilla. Departamento de Electrónica y Electromagnetismo |
Fecha de publicación | 1992 |
Fecha de depósito | 2020-03-20 |
Publicado en |
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Resumen | A 3-μm CMOS IC is presented demonstrating the concept of an analog neural system for constrained optimization. A serial time-multiplexed general-purpose architecture is introduced for the real-time solution of this kind ... A 3-μm CMOS IC is presented demonstrating the concept of an analog neural system for constrained optimization. A serial time-multiplexed general-purpose architecture is introduced for the real-time solution of this kind of problem in MOS VLSI. This architecture is a fully programmable and reconfigurable one exploiting SC techniques for the analog part and making extensive use of digital techniques for programmability. |
Cita | Domínguez Castro, R., Rodríguez Vázquez, Á.B., Huertas Díaz, J.L. y Sánchez Sinencio, E. (1992). Analog Neural Programmable Optimizers in CMOS VLSI Technologies. IEEE Journal of Solid-State Circuits, 27 (7), 1110-1115. |
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