Ponencia
A processing element architecture for high-density focal plane analog programmable array processors
Autor/es | Liñán Cembrano, Gustavo
Espejo Meana, Servando Carlos Domínguez Castro, Rafael Rodríguez Vázquez, Ángel Benito |
Departamento | Universidad de Sevilla. Departamento de Electrónica y Electromagnetismo |
Fecha de publicación | 2002 |
Fecha de depósito | 2020-01-30 |
Publicado en |
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ISBN/ISSN | 0-7803-7448-7 0271-4310 |
Resumen | The architecture of the elementary Processing Element - PE- used in a recently designed 128×128 Focal Plane Analog Programmable Array Processor is presented. The PE architecture contains the required building blocks to ... The architecture of the elementary Processing Element - PE- used in a recently designed 128×128 Focal Plane Analog Programmable Array Processor is presented. The PE architecture contains the required building blocks to implement bifurcated data flow vision algorithms based on the execution of 3 × 3 convolution masks. The vision chip has been implemented in a standard 0.35μm CMOS technology. The main PE related figures are: 180 cells/mm2, 18 MOPS/cell, and 180 μW/cell. |
Identificador del proyecto | N68171-98-C-9004
IST-1999-19007 TIC1 999-0826 |
Cita | Liñán Cembrano, G., Espejo Meana, S.C., Domínguez Castro, R. y Rodríguez Vázquez, Á.B. (2002). A processing element architecture for high-density focal plane analog programmable array processors. En International Symposium on Circuits and Systems (ISCAS) (III-341-III-344), Phoenix-Scottsdale, USA: Institute of Electrical and Electronics Engineers. |
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