Ponencia
Event-based Row-by-Row Multi-convolution engine for Dynamic-Vision Feature Extraction on FPGA
Autor/es | Tapiador Morales, Ricardo
Ríos Navarro, José Antonio Domínguez Morales, Juan Pedro Gutiérrez Galán, Daniel Domínguez Morales, Manuel Jesús Jiménez Fernández, Ángel Francisco Linares Barranco, Alejandro |
Departamento | Universidad de Sevilla. Departamento de Arquitectura y Tecnología de Computadores |
Fecha de publicación | 2018 |
Fecha de depósito | 2020-01-22 |
Publicado en |
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ISBN/ISSN | 978-1-5090-6014-6 2161-4407 |
Resumen | Neural networks algorithms are commonly used to
recognize patterns from different data sources such as audio or
vision. In image recognition, Convolutional Neural Networks are
one of the most effective techniques due ... Neural networks algorithms are commonly used to recognize patterns from different data sources such as audio or vision. In image recognition, Convolutional Neural Networks are one of the most effective techniques due to the high accuracy they achieve. This kind of algorithms require billions of addition and multiplication operations over all pixels of an image. However, it is possible to reduce the number of operations using other computer vision techniques rather than frame-based ones, e.g. neuromorphic frame-free techniques. There exists many neuromorphic vision sensors that detect pixels that have changed their luminosity. In this study, an event-based convolution engine for FPGA is presented. This engine models an array of leaky integrate and fire neurons. It is able to apply different kernel sizes, from 1x1 to 7x7, which are computed row by row, with a maximum number of 64 different convolution kernels. The design presented is able to process 64 feature maps of 7x7 with a latency of 8.98 s. |
Identificador del proyecto | TEC2016-77785-P |
Cita | Tapiador Morales, R., Rios Navarro, A., Domínguez Morales, J.P., Gutiérrez Galán, D., Domínguez Morales, M.J., Jiménez Fernández, Á.F. y Linares Barranco, A. (2018). Event-based Row-by-Row Multi-convolution engine for Dynamic-Vision Feature Extraction on FPGA. En IJCNN 2018 : International Joint Conference on Neural Networks Rio de Janeiro, Brazil: IEEE Computer Society. |
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