Presentation
FPGA Implementations Comparison of Neuro-cortical Inspired Convolution Processors for Spiking Systems
Author/s | Linares Barranco, Alejandro
![]() ![]() ![]() ![]() ![]() ![]() ![]() Paz Vicente, Rafael ![]() ![]() ![]() ![]() ![]() ![]() ![]() Gómez Rodríguez, Francisco de Asís ![]() ![]() ![]() ![]() ![]() ![]() ![]() Jiménez Fernández, Ángel Francisco ![]() ![]() ![]() ![]() ![]() ![]() ![]() Rivas Pérez, Manuel ![]() ![]() ![]() ![]() ![]() ![]() ![]() Jiménez Moreno, Gabriel ![]() ![]() ![]() ![]() ![]() ![]() ![]() Civit Balcells, Antón ![]() ![]() ![]() ![]() ![]() ![]() ![]() |
Department | Universidad de Sevilla. Departamento de Arquitectura y Tecnología de Computadores |
Publication Date | 2009 |
Deposit Date | 2019-12-17 |
Published in |
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ISBN/ISSN | 978-3-642-02477-1 0302-9743 |
Abstract | Image convolution operations in digital computer systems are usually
very expensive operations in terms of resource consumption (processor
resources and processing time) for an efficient Real-Time application. In ... Image convolution operations in digital computer systems are usually very expensive operations in terms of resource consumption (processor resources and processing time) for an efficient Real-Time application. In these scenarios the visual information is divided in frames and each one has to be completely processed before the next frame arrives. Recently a new method for computing convolutions based on the neuro-inspired philosophy of spiking systems (Address-Event-Representation systems, AER) is achieving high performances. In this paper we present two FPGA implementations of AERbased convolution processors that are able to work with 64x64 images and programmable kernels of up to 11x11 elements. The main difference is the use of RAM for integrators in one solution and the absence of integrators in the second solution that is based on mapping operations. The maximum equivalent operation rate is 163.51 MOPS for 11x11 kernels, in a Xilinx Spartan 3 400 FPGA with a 50MHz clock. Formulations, hardware architecture, operation examples and performance comparison with frame-based convolution processors are presented and discussed. |
Project ID. | TEC2006-11730-C03-02
![]() P06-TIC-01417 ![]() |
Citation | Linares Barranco, A., Paz Vicente, R., Gómez Rodríguez, F.d.A., Jiménez Fernández, Á.F., Rivas Pérez, M., Jiménez Moreno, G. y Civit Balcells, A. (2009). FPGA Implementations Comparison of Neuro-cortical Inspired Convolution Processors for Spiking Systems. En IWANN 2009: 10th International Work-Conference on Artificial Neural Networks (97-105), Salamanca, España: Springer. |
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