Article
Accurate Settling-Time Modeling and Design Procedures for Two-Stage Miller-Compensated Amplifiers for Switched-Capacitor Circuits
Author/s | Ruiz Amaya, Jesús
Delgado Restituto, Manuel Rodríguez Vázquez, Ángel Benito |
Department | Universidad de Sevilla. Departamento de Electrónica y Electromagnetismo |
Publication Date | 2009 |
Deposit Date | 2019-11-26 |
Published in |
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Abstract | We present modeling techniques for accurate estimation of settling errors in switched-capacitor (SC) circuits built with Miller-compensated operational transconductance amplifiers (OTAs). One distinctive feature of the ... We present modeling techniques for accurate estimation of settling errors in switched-capacitor (SC) circuits built with Miller-compensated operational transconductance amplifiers (OTAs). One distinctive feature of the proposal is the computation of the impact of signal levels (on both the model parameters and the model structure) as they change during transient evolution. This is achieved by using an event-driven behavioral approach that combines small- and large-signal behavioral descriptions and keeps track of the amplifier state after each clock phase. Also, SC circuits are modeled under closed-loop conditions to guarantee that the results remain close to those obtained by electrical simulation of the actual circuits. Based on these models, which can be regarded as intermediate between the more established small-signal approach and full-fledged simulations, design procedures for dimensioning SC building blocks are presented whose targets are system-level specifications (such as ENOB and SNDR) instead of OTA specifications. The proposed techniques allow to complete top-down model-based designs with 0.3-b accuracy. |
Project ID. | TEC2006-03022
TIC-02818 |
Citation | Ruiz Amaya, J., Delgado Restituto, M. y Rodríguez Vázquez, Á.B. (2009). Accurate Settling-Time Modeling and Design Procedures for Two-Stage Miller-Compensated Amplifiers for Switched-Capacitor Circuits. IEEE Transactions on Circuits and Systems I: Regular Papers, 56 (6), 1077-1087. |
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Accurate Settling-Time Modeling.pdf | 1.340Mb | [PDF] | View/ | |