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dc.creatorRodríguez Pérez, Albertoes
dc.creatorRuiz Amaya, Jesúses
dc.creatorRodríguez Rodríguez, José Antonioes
dc.creatorDelgado Restituto, Manueles
dc.creatorRodríguez Vázquez, Ángel Benitoes
dc.date.accessioned2019-11-06T14:40:11Z
dc.date.available2019-11-06T14:40:11Z
dc.date.issued2011
dc.identifier.citationRodríguez Pérez, A., Ruiz Amaya, J., Rodríguez Rodríguez, J.A., Delgado Restituto, M. y Rodríguez Vázquez, Á.B. (2011). A power efficient neural spike recording channel with data bandwidth reduction. En IEEE International Symposium of Circuits and Systems (ISCAS) (1704-1707), Río de Janeiro, Brasil: Institute of Electrical and Electronics Engineers.
dc.identifier.isbn978-1-4244-9473-6es
dc.identifier.issn0271-4302es
dc.identifier.urihttps://hdl.handle.net/11441/90048
dc.description.abstractThis paper presents a mixed-signal neural spike recording channel which features, as an added value, a simple and low-power data compression mechanism. The channel uses a band-limited differential low noise amplifier and a binary search data converter, together with other digital and analog blocks for control, programming and spike characterization. The channel offers a self-calibration operation mode and it can be configured both for signal tracking (to raw digitize the acquired neural waveform) and feature extraction (to build a first-order PWL approximation of the spikes). The prototype has been fabricated in a standard CMOS 0.13μm and occupies 400μm×400μm. The overall power consumption of the channel during signal tracking is 2.8μW and increases to 3.0μW average when the feature extraction operation mode is programmed.es
dc.description.sponsorshipMinisterio de Ciencia e Innovación TEC2009-08447es
dc.description.sponsorshipJunta de Andalucía TIC-02818es
dc.formatapplication/pdfes
dc.language.isoenges
dc.publisherInstitute of Electrical and Electronics Engineerses
dc.relation.ispartofIEEE International Symposium of Circuits and Systems (ISCAS) (2011), p 1704-1707
dc.rightsAttribution-NonCommercial-NoDerivatives 4.0 Internacional*
dc.rights.urihttp://creativecommons.org/licenses/by-nc-nd/4.0/*
dc.titleA power efficient neural spike recording channel with data bandwidth reductiones
dc.typeinfo:eu-repo/semantics/conferenceObjectes
dc.type.versioninfo:eu-repo/semantics/acceptedVersiones
dc.rights.accessRightsinfo:eu-repo/semantics/openAccesses
dc.contributor.affiliationUniversidad de Sevilla. Departamento de Electrónica y Electromagnetismoes
dc.relation.projectIDTEC2009-08447es
dc.relation.projectIDTIC-02818es
dc.relation.publisherversionhttps://doi.org/10.1109/ISCAS.2011.5937910es
dc.identifier.doi10.1109/ISCAS.2011.5937910es
idus.format.extent4 p.es
dc.publication.initialPage1704es
dc.publication.endPage1707es
dc.eventtitleIEEE International Symposium of Circuits and Systems (ISCAS)es
dc.eventinstitutionRío de Janeiro, Brasiles
dc.identifier.sisius20128382es

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