dc.creator | Rodríguez Pérez, Alberto | es |
dc.creator | Ruiz Amaya, Jesús | es |
dc.creator | Rodríguez Rodríguez, José Antonio | es |
dc.creator | Delgado Restituto, Manuel | es |
dc.creator | Rodríguez Vázquez, Ángel Benito | es |
dc.date.accessioned | 2019-11-06T14:40:11Z | |
dc.date.available | 2019-11-06T14:40:11Z | |
dc.date.issued | 2011 | |
dc.identifier.citation | Rodríguez Pérez, A., Ruiz Amaya, J., Rodríguez Rodríguez, J.A., Delgado Restituto, M. y Rodríguez Vázquez, Á.B. (2011). A power efficient neural spike recording channel with data bandwidth reduction. En IEEE International Symposium of Circuits and Systems (ISCAS) (1704-1707), Río de Janeiro, Brasil: Institute of Electrical and Electronics Engineers. | |
dc.identifier.isbn | 978-1-4244-9473-6 | es |
dc.identifier.issn | 0271-4302 | es |
dc.identifier.uri | https://hdl.handle.net/11441/90048 | |
dc.description.abstract | This paper presents a mixed-signal neural spike recording channel which features, as an added value, a simple and low-power data compression mechanism. The channel uses a band-limited differential low noise amplifier and a binary search data converter, together with other digital and analog blocks for control, programming and spike characterization. The channel offers a self-calibration operation mode and it can be configured both for signal tracking (to raw digitize the acquired neural waveform) and feature extraction (to build a first-order PWL approximation of the spikes). The prototype has been fabricated in a standard CMOS 0.13μm and occupies 400μm×400μm. The overall power consumption of the channel during signal tracking is 2.8μW and increases to 3.0μW average when the feature extraction operation mode is programmed. | es |
dc.description.sponsorship | Ministerio de Ciencia e Innovación TEC2009-08447 | es |
dc.description.sponsorship | Junta de Andalucía TIC-02818 | es |
dc.format | application/pdf | es |
dc.language.iso | eng | es |
dc.publisher | Institute of Electrical and Electronics Engineers | es |
dc.relation.ispartof | IEEE International Symposium of Circuits and Systems (ISCAS) (2011), p 1704-1707 | |
dc.rights | Attribution-NonCommercial-NoDerivatives 4.0 Internacional | * |
dc.rights.uri | http://creativecommons.org/licenses/by-nc-nd/4.0/ | * |
dc.title | A power efficient neural spike recording channel with data bandwidth reduction | es |
dc.type | info:eu-repo/semantics/conferenceObject | es |
dc.type.version | info:eu-repo/semantics/acceptedVersion | es |
dc.rights.accessRights | info:eu-repo/semantics/openAccess | es |
dc.contributor.affiliation | Universidad de Sevilla. Departamento de Electrónica y Electromagnetismo | es |
dc.relation.projectID | TEC2009-08447 | es |
dc.relation.projectID | TIC-02818 | es |
dc.relation.publisherversion | https://doi.org/10.1109/ISCAS.2011.5937910 | es |
dc.identifier.doi | 10.1109/ISCAS.2011.5937910 | es |
idus.format.extent | 4 p. | es |
dc.publication.initialPage | 1704 | es |
dc.publication.endPage | 1707 | es |
dc.eventtitle | IEEE International Symposium of Circuits and Systems (ISCAS) | es |
dc.eventinstitution | Río de Janeiro, Brasil | es |
dc.identifier.sisius | 20128382 | es |