Presentation
Electrical-level synthesis of pipeline ADCs
Author/s | Ruiz Amaya, Jesús
Delgado Restituto, Manuel Rodríguez Vázquez, Ángel Benito |
Department | Universidad de Sevilla. Departamento de Electrónica y Electromagnetismo |
Publication Date | 2008 |
Deposit Date | 2019-10-25 |
Published in |
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ISBN/ISSN | 978-1-4244-2341-5 |
Abstract | This paper presents a design tool for the synthesis of pipeline ADCs which is able to optimally map high-level converter specifications, such as the required effective resolution, onto electrical-level parameters, i.e., ... This paper presents a design tool for the synthesis of pipeline ADCs which is able to optimally map high-level converter specifications, such as the required effective resolution, onto electrical-level parameters, i.e., transistor sizes and biasing conditions. It is based on the combination of a behavioural simulator for performance evaluation, accurate models of the converter components, and an optimization algorithm to minimize the power and area consumption of the circuit solution. The design procedure is herein demonstrated with the complete design of a 0.13 mum CMOS 10 bits@60MS/s pipeline ADC, which only consumes 11.3 mW from a 1.2 V supply voltage. A close agreement between behavioural- and electrical-level simulations is obtained with only 0.2 bit deviation on the measured ENOB. |
Project ID. | TEC2006-03022
TIC-02818 |
Citation | Ruiz Amaya, J., Delgado Restituto, M. y Rodríguez Vázquez, Á.B. (2008). Electrical-level synthesis of pipeline ADCs. En IEEE Asia Pacific Conference on Circuits and Systems (1628-1631), Macao, China: Institute of Electrical and Electronics Engineers. |
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Electrical-level synthesis.pdf | 824.6Kb | [PDF] | View/ | |