Presentation
High-performance ΣΔ ADC for ADSL applications in 0.35μm CMOS digital technology
Author/s | Río Fernández, Rocío del
![]() ![]() ![]() ![]() ![]() ![]() ![]() Rosa Utrera, José Manuel de la ![]() ![]() ![]() ![]() ![]() ![]() ![]() Medeiro Hidalgo, Fernando Pérez Verdú, Belén Rodríguez Vázquez, Ángel Benito ![]() ![]() ![]() ![]() ![]() ![]() ![]() |
Department | Universidad de Sevilla. Departamento de Electrónica y Electromagnetismo |
Publication Date | 2001 |
Deposit Date | 2019-10-01 |
Published in |
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ISBN/ISSN | 0-7803-7057-0 |
Abstract | We present a ΣΔ modulator designed for ADSL applications in a 0.3Sμm CMOS pure digital technology. It employs a 4th-order 3-stage cascade architecture including both single-bit and multi-bit quantizers with programmable ... We present a ΣΔ modulator designed for ADSL applications in a 0.3Sμm CMOS pure digital technology. It employs a 4th-order 3-stage cascade architecture including both single-bit and multi-bit quantizers with programmable resolution, which allows us to use only 16 oversampling ratio. Especial emphasis is placed on technology issues, namely: poor analog performance and substrate coupling. The measured performances are 13-bit dynamic range operating at 2MS/s and 12-bit dynamic range operating at 4MS/s. The modulator consumes 77mW from a 3.3-V supply and occupies 1.32 mm2. |
Citation | Río Fernández, R.d., Rosa Utrera, J.M.d.l., Medeiro Hidalgo, F., Pérez Verdú, B. y Rodríguez Vázquez, Á.B. (2001). High-performance ΣΔ ADC for ADSL applications in 0.35μm CMOS digital technology. En 8th IEEE International Conference on Electronics, Circuits and Systems (501-504), Malta: Institute of Electrical and Electronics Engineers. |
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