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Digital processor array implementation aspects of a 3D multi-layer vision architecture

dc.creatorFöldesy, Peteres
dc.creatorCarmona Galán, Ricardoes
dc.creatorRekeczky, Csabaes
dc.creatorZarandy, A.es
dc.creatorRodríguez Vázquez, Ángel Benitoes
dc.creatorRoska, Tamáses
dc.date.accessioned2019-09-03T13:58:42Z
dc.date.available2019-09-03T13:58:42Z
dc.date.issued2010
dc.identifier.citationFöldesy, P., Carmona Galán, R., Rekeczky, C., Zarandy, A., Rodríguez Vázquez, Á.B. y Roska, T. (2010). Digital processor array implementation aspects of a 3D multi-layer vision architecture. En 12th International Workshop on Cellular Nanoscale Networks and Their Applications (CNNA) (1-4), Berkeley (USA): Institute of Electrical and Electronics Engineers.
dc.identifier.isbn978-1-4244-6679-5es
dc.identifier.urihttps://hdl.handle.net/11441/88927
dc.description.abstractTechnological aspects of the 3D integration of a multilayer combined mixed-signal and digital sensor-processor array chip is described. The 3D integration raises the question of signal routing, power distribution, and heat dissipation, which aspects are considered systematically in the digital processor array layer as part of the multi layer structure. We have developed a linear programming based evaluation system to identify the proper architecture and its parameters.es
dc.description.sponsorshipOffice of Naval Research N00173-08-C-4005 VISCUBEes
dc.formatapplication/pdfes
dc.language.isoenges
dc.publisherInstitute of Electrical and Electronics Engineerses
dc.relation.ispartof12th International Workshop on Cellular Nanoscale Networks and Their Applications (CNNA) (2010), p 1-4
dc.rightsAttribution-NonCommercial-NoDerivatives 4.0 Internacional*
dc.rights.urihttp://creativecommons.org/licenses/by-nc-nd/4.0/*
dc.subject3D integrationes
dc.subjectUAV navigationes
dc.subjectSensor-processores
dc.titleDigital processor array implementation aspects of a 3D multi-layer vision architecturees
dc.typeinfo:eu-repo/semantics/conferenceObjectes
dcterms.identifierhttps://ror.org/03yxnpp24
dc.type.versioninfo:eu-repo/semantics/acceptedVersiones
dc.rights.accessRightsinfo:eu-repo/semantics/openAccesses
dc.contributor.affiliationUniversidad de Sevilla. Departamento de Electrónica y Electromagnetismoes
dc.relation.projectIDN00173-08-C-4005 VISCUBEes
dc.relation.publisherversionhttp://dx.doi.org/10.1109/CNNA.2010.5430274es
dc.identifier.doi10.1109/CNNA.2010.5430274es
idus.format.extent4 p.es
dc.publication.initialPage1es
dc.publication.endPage4es
dc.eventtitle12th International Workshop on Cellular Nanoscale Networks and Their Applications (CNNA)es
dc.eventinstitutionBerkeley (USA)es
dc.identifier.sisius5436240es

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Except where otherwise noted, this item's license is described as: Attribution-NonCommercial-NoDerivatives 4.0 Internacional