Presentation
ACE16k: A programmable focal plane vision processor with 128 x 128 resolution
Author/s | Liñán Cembrano, Gustavo
Domínguez Castro, Rafael Espejo Meana, Servando Carlos Rodríguez Vázquez, Ángel Benito |
Department | Universidad de Sevilla. Departamento de Electrónica y Electromagnetismo |
Publication Date | 2001 |
Deposit Date | 2018-10-03 |
Published in |
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Abstract | This paper presents a new generation
128x128 Focal Plane Analog Programmable
Array Processor (FPAPAP), from a system level
perspective. The design has recently sent to fabrication
in a 0.35μm standard digital 1P-5M ... This paper presents a new generation 128x128 Focal Plane Analog Programmable Array Processor (FPAPAP), from a system level perspective. The design has recently sent to fabrication in a 0.35μm standard digital 1P-5M CMOS Technology. The chip has been designed to achieve the high-speed and moderate-accuracy constraints of most real time image processing applications. It has been designed to be easily embedded in conventional digital hosting systems: external data interchange and control are completely digital. The chip contains close to four millions transistors, 80% of them working in analog mode, and exhibits a relatively low power consumption (<4W, i.e. less than 1mW per transistor). Experimental results are expected for the date of paper presentation. |
Citation | Liñán Cembrano, G., Domínguez Castro, R., Espejo Meana, S.C. y Rodríguez Vázquez, Á.B. (2001). ACE16k: A programmable focal plane vision processor with 128 x 128 resolution. En European Conference on Circuit Theory and Design: "Circuit Paradigm in the 21st Century" (1-4), Finlandia: European Conference on Circuit Theory and Design. |
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ACE16k.pdf | 117.3Kb | [PDF] | View/ | |