Artículo
Multi-bit cascade ΣΔ modulator for high-speed A/D conversion with reduced sensitivity to DAC errors
Autor/es | Medeiro Hidalgo, Fernando
Pérez Verdú, Belén Rosa Utrera, José Manuel de la Rodríguez Vázquez, Ángel Benito |
Departamento | Universidad de Sevilla. Departamento de Electrónica y Electromagnetismo |
Fecha de publicación | 1998 |
Fecha de depósito | 2018-07-24 |
Publicado en |
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Resumen | This paper presents a ΣΔ modulator (ΣΔM) which combines single-bit and multi-bit quantization in a cascade architecture to obtain high resolution with low oversampling ratio. It is less sensitive to the non-linearity of ... This paper presents a ΣΔ modulator (ΣΔM) which combines single-bit and multi-bit quantization in a cascade architecture to obtain high resolution with low oversampling ratio. It is less sensitive to the non-linearity of the DAC than those previously reported, thus enabling the use of very simple analog circuitry with neither calibration nor trimming required. |
Agencias financiadoras | Comisión Interministerial de Ciencia y Tecnología (CICYT). España |
Identificador del proyecto | TIC97-0580 |
Cita | Medeiro Hidalgo, F., Pérez Verdú, B., Rosa Utrera, J.M.d.l. y Rodríguez Vázquez, Á.B. (1998). Multi-bit cascade ΣΔ modulator for high-speed A/D conversion with reduced sensitivity to DAC errors. Electronics Letters, 34 (5), 422-424. |
Ficheros | Tamaño | Formato | Ver | Descripción |
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Multi-bit Cascade ΣΔ Modulator.pdf | 1.126Mb | [PDF] | Ver/ | |