dc.creator | Serrano Gotarredona, María Teresa | es |
dc.creator | Linares Barranco, Bernabé | es |
dc.date.accessioned | 2018-06-26T13:18:43Z | |
dc.date.available | 2018-06-26T13:18:43Z | |
dc.date.issued | 1997 | |
dc.identifier.citation | Serrano Gotarredona, M.T. y Linares Barranco, B. (1997). An ART1 microchip and its use in multi-ART1 systems. IEEE Transactions on Neural Networks, 8 (5), 1184-1194. | |
dc.identifier.issn | 1045-9227 | es |
dc.identifier.uri | https://hdl.handle.net/11441/76476 | |
dc.description.abstract | Recently, a real-time clustering microchip neural engine based on the ART1 architecture has been reported. Such chip is able to cluster 100-b patterns into up to 18 categories at a speed of 1.8 μs per pattern. However, that chip rendered an extremely high silicon area consumption of 1 cm2, and consequently an extremely low yield of 6%. Redundant circuit techniques can be introduced to improve yield performance at the cost of further increasing chip size. In this paper we present an improved ART1 chip prototype based on a different approach to implement the most area consuming circuit elements of the first prototype: an array of several thousand current sources which have to match within a precision of around 1%. Such achievement was possible after a careful transistor mismatch characterization of the fabrication process (ES2-1.0 μm CMOS). A new prototype chip has been fabricated which can cluster 50-b input patterns into up to ten categories. The chip has 15 times less area, shows a yield performance of 98%, and presents the same precision and speed than the previous prototype. Due to its higher robustness multichip systems are easily assembled. As a demonstration we show results of a two-chip ART1 system, and of an ARTMAP system made of two ART1 chips and an extra interfacing chip. | es |
dc.format | application/pdf | es |
dc.language.iso | eng | es |
dc.publisher | Institute of Electrical and Electronics Engineers | es |
dc.relation.ispartof | IEEE Transactions on Neural Networks, 8 (5), 1184-1194. | |
dc.rights | Attribution-NonCommercial-NoDerivatives 4.0 Internacional | * |
dc.rights.uri | http://creativecommons.org/licenses/by-nc-nd/4.0/ | * |
dc.title | An ART1 microchip and its use in multi-ART1 systems | es |
dc.type | info:eu-repo/semantics/article | es |
dcterms.identifier | https://ror.org/03yxnpp24 | |
dc.type.version | info:eu-repo/semantics/acceptedVersion | es |
dc.rights.accessRights | info:eu-repo/semantics/openAccess | es |
dc.contributor.affiliation | Universidad de Sevilla. Departamento de Arquitectura y Tecnología de Computadores | es |
dc.relation.publisherversion | http://dx.doi.org/10.1109/72.623219 | es |
dc.identifier.doi | 10.1109/72.623219 | es |
idus.format.extent | 11 p. | es |
dc.journaltitle | IEEE Transactions on Neural Networks | es |
dc.publication.volumen | 8 | es |
dc.publication.issue | 5 | es |
dc.publication.initialPage | 1184 | es |
dc.publication.endPage | 1194 | es |