Ponencia
An ultra-low-power voltage-mode asynchronous WTA-LTA circuit
Autor/es | Fernández Berni, Jorge
Carmona Galán, Ricardo Rodríguez Vázquez, Ángel Benito |
Departamento | Universidad de Sevilla. Departamento de Electrónica y Electromagnetismo |
Fecha de publicación | 2013 |
Fecha de depósito | 2018-06-01 |
Publicado en |
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ISBN/ISSN | 978-1-4673-5762-3 (electrónico) 978-1-4673-5760-9 (impreso) |
Resumen | This paper presents an asynchronous mixed-signal
WTA-LTA circuit conceived to carry out local minimummaximum
indexing in massively parallel image processing arrays.
The hardware is focused on energy-efficient operation. ... This paper presents an asynchronous mixed-signal WTA-LTA circuit conceived to carry out local minimummaximum indexing in massively parallel image processing arrays. The hardware is focused on energy-efficient operation. We describe a realization for the standard CMOS base process of a commercial 3-D TSV stack featuring a power consumption of only 20pW per elementary cell at 30fps. The proposed block is also capable of resolving small voltage differences without requiring any external reference. This leads to a hit percentage greater than 90% even when taking into account global process variations and mismatch conditions. |
Agencias financiadoras | Ministerio de Economía y Competitividad (MINECO). España European Commission (EC). Fondo Europeo de Desarrollo Regional (FEDER) |
Identificador del proyecto | TEC2012-38921-C02-01
IPT-2011-1625- 430000 IPC-20111009 |
Cita | Fernández Berni, J., Carmona Galán, R. y Rodríguez Vázquez, Á.B. (2013). An ultra-low-power voltage-mode asynchronous WTA-LTA circuit. En IEEE International Symposium on Circuits and Systems (ISCAS) (1-4), Beijing, China: Institute of Electrical and Electronics Engineers. |
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