dc.creator | Yousefzadeh, Amirreza | es |
dc.creator | Jabłonski, M. | es |
dc.creator | Iakymchuk, T. | es |
dc.creator | Linares Barranco, Alejandro | es |
dc.creator | Rosado, Alfredo | es |
dc.creator | Plana, Luis A. | es |
dc.creator | Temple, Steve | es |
dc.creator | Serrano Gotarredona, María Teresa | es |
dc.creator | Furber, Steve B. | es |
dc.creator | Linares Barranco, Bernabé | es |
dc.date.accessioned | 2018-04-12T14:28:12Z | |
dc.date.available | 2018-04-12T14:28:12Z | |
dc.date.issued | 2017 | |
dc.identifier.citation | Yousefzadeh, A., Jabłonski, M., Iakymchuk, T., Linares Barranco, A., Rosado, A., Plana, L.A.,...,Linares Barranco, B. (2017). On Multiple AER Handshaking Channels Over High-Speed Bit-Serial Bidirectional LVDS Links With Flow-Control and Clock-Correction on Commercial FPGAs for Scalable Neuromorphic Systems. IEEE Transactions on Biomedical Circuits and Systems, 11 (5), 1133-1147. | |
dc.identifier.issn | 1932-4545 (impreso) | es |
dc.identifier.issn | 1940-9990 (electrónico) | es |
dc.identifier.uri | https://hdl.handle.net/11441/72615 | |
dc.description.abstract | Address event representation (AER) is a widely employed asynchronous technique for interchanging “neural spikes” between different hardware elements in neuromorphic systems. Each neuron or cell in a chip or a system is assigned an address (or ID), which is typically communicated through a high-speed digital bus, thus time-multiplexing a high number of neural connections. Conventional AER links use parallel physical wires together with a pair of handshaking signals (request and acknowledge). In this paper, we present a fully serial implementation using bidirectional SATA connectors with a pair of low-voltage differential signaling (LVDS) wires for each direction. The proposed implementation can multiplex a number of conventional parallel AER links for each physical LVDS connection. It uses flow control, clock correction, and byte alignment techniques to transmit 32-bit address events reliably over multiplexed serial connections. The setup has been tested using commercial Spartan6 FPGAs attaining a maximum event transmission speed of 75 Meps (Mega events per second) for 32-bit events at a line rate of 3.0 Gbps. Full HDL codes (vhdl/verilog) and example demonstration codes for the SpiNNaker platform will be made available. | es |
dc.description.sponsorship | European Union 320689, 604102, 644096, 687299 | es |
dc.description.sponsorship | U.K. Engineering and Physical Sciences Research Council EP/G015740/1 | es |
dc.description.sponsorship | Polish Ministry of Science and Higher Education 11.11.120.612 | es |
dc.description.sponsorship | Ministerio de Economía y Competitividad TEC2012-37868-C04-01/02 , TEC2015- 63884-C2-1-P, TEC2016-77785-P | es |
dc.description.sponsorship | Junta de Andalucía TIC-6091, P12-TIC-1300 | es |
dc.format | application/pdf | es |
dc.language.iso | eng | es |
dc.publisher | Institute of Electrical and Electronics Engineers | es |
dc.relation.ispartof | IEEE Transactions on Biomedical Circuits and Systems, 11 (5), 1133-1147. | |
dc.rights | Attribution-NonCommercial-NoDerivatives 4.0 Internacional | * |
dc.rights.uri | http://creativecommons.org/licenses/by-nc-nd/4.0/ | * |
dc.title | On Multiple AER Handshaking Channels Over High-Speed Bit-Serial Bidirectional LVDS Links With Flow-Control and Clock-Correction on Commercial FPGAs for Scalable Neuromorphic Systems | es |
dc.type | info:eu-repo/semantics/article | es |
dcterms.identifier | https://ror.org/03yxnpp24 | |
dc.type.version | info:eu-repo/semantics/acceptedVersion | es |
dc.rights.accessRights | info:eu-repo/semantics/openAccess | es |
dc.contributor.affiliation | Universidad de Sevilla. Departamento de Arquitectura y Tecnología de Computadores | es |
dc.relation.projectID | 320689 | es |
dc.relation.projectID | 604102 | es |
dc.relation.projectID | 644096 | es |
dc.relation.projectID | 687299 | es |
dc.relation.projectID | EP/G015740/1 | es |
dc.relation.projectID | 11.11.120.612 | es |
dc.relation.projectID | TEC2012-37868-C04-01/02 | es |
dc.relation.projectID | TEC2015- 63884-C2-1-P | es |
dc.relation.projectID | TEC2016-77785-P | es |
dc.relation.projectID | TIC-6091 | es |
dc.relation.projectID | P12-TIC-1300 | es |
dc.relation.publisherversion | https://doi.org/10.1109/TBCAS.2017.2717341 | es |
dc.identifier.doi | 10.1109/TBCAS.2017.2717341 | es |
idus.format.extent | 15 p. | es |
dc.journaltitle | IEEE Transactions on Biomedical Circuits and Systems | es |
dc.publication.volumen | 11 | es |
dc.publication.issue | 5 | es |
dc.publication.initialPage | 1133 | es |
dc.publication.endPage | 1147 | es |