Ponencia
Selective Clock-Gating for Low Power/Low Noise Synchronous Counters
Autor/es | Parra Fernández, María del Pilar
Acosta Jiménez, Antonio José Valencia Barrero, Manuel |
Departamento | Universidad de Sevilla. Departamento de Tecnología Electrónica Universidad de Sevilla. Departamento de Electrónica y Electromagnetismo |
Fecha de publicación | 2002 |
Fecha de depósito | 2017-10-04 |
Publicado en |
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ISBN/ISSN | 978-3-540-44143-4 0302-9743 |
Resumen | The objective of this paper is to explore the applicability of clock
gating techniques to binary counters in order to reduce the power consumption
as well as the switching noise generation. A measurement methodology
to ... The objective of this paper is to explore the applicability of clock gating techniques to binary counters in order to reduce the power consumption as well as the switching noise generation. A measurement methodology to establish right comparisons between different implementations of gateclocked counters is presented. Basically two ways of applying clock gating are considered: clock gating on independent bits and clock gating on groups of bits. The right selection of bits where clock gating must be applied and the suited composition of groups of bits is essential when applying this technique. We have found groupment of bits is the best option when applying clock gating to reduce power consumption and specially to reduce noise generation. |
Agencias financiadoras | Ministerio de Ciencia y Tecnología (MCYT). España |
Identificador del proyecto | TIC2000-1350
TIC2001- 2283 |
Cita | Parra Fernández, M.d.P., Acosta, A. y Valencia Barrero, M. (2002). Selective Clock-Gating for Low Power/Low Noise Synchronous Counters. En PATMOS 2002 : 12th International Workshop on Power and Timing Modeling, Optimization and Simulation (448-457), Sevilla, España: Springer. |
Ficheros | Tamaño | Formato | Ver | Descripción |
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Selective Clock-Gating.pdf | 2.507Mb | [PDF] | Ver/ | |