Ponencia
Fault Attack on FPGA implementations of Trivium Stream Cipher
Autor/es | Potestad Ordóñez, Francisco Eugenio
Jiménez Fernández, Carlos Jesús Valencia Barrero, Manuel |
Departamento | Universidad de Sevilla. Departamento de Tecnología Electrónica |
Fecha de publicación | 2016 |
Fecha de depósito | 2017-10-03 |
Publicado en |
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ISBN/ISSN | 978-1-4799-5341-7 2379-447X |
Resumen | This article presents the development of an experimental
system to introduce faults in Trivium stream ciphers
implemented on FPGA. The developed system has made possible
to analyze the vulnerability of these implementations ... This article presents the development of an experimental system to introduce faults in Trivium stream ciphers implemented on FPGA. The developed system has made possible to analyze the vulnerability of these implementations against fault attacks. The developed system consists of a mechanism that injects small pulses in the clock signal, and elements that analyze if a fault has been introduced, the number of faults introduced and its position in the inner state. The results obtained demonstrate the vulnerability of these implementations against fault attacks. As far as we know, this is the first time that experimental results of fault attack over Trivium are presented. |
Identificador del proyecto | info:eu-repo/grantAgreement/MINECO/TEC2010-16870
info:eu-repo/grantAgreement/MINECO/TEC2013-45523-R info:eu-repo/grantAgreement/MINECO/201550E039 |
Cita | Potestad Ordóñez, F.E., Jiménez Fernández, C.J. y Valencia Barrero, M. (2016). Fault Attack on FPGA implementations of Trivium Stream Cipher. En ISCAS 2016 : IEEE International Symposium on Circuits and Systems (562-565), Montreal, QC, Canada: IEEE Computer Society. |
Ficheros | Tamaño | Formato | Ver | Descripción |
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Fault attack.pdf | 206.9Kb | [PDF] | Ver/ | |